Patents by Inventor Jung-Cheun Lien
Jung-Cheun Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8258811Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: June 10, 2011Date of Patent: September 4, 2012Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Publication number: 20110234258Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: ApplicationFiled: June 10, 2011Publication date: September 29, 2011Applicant: ACTEL CORPORATIONInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 7977970Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: June 4, 2010Date of Patent: July 12, 2011Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Publication number: 20100244894Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: ApplicationFiled: June 4, 2010Publication date: September 30, 2010Inventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 7755386Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: April 29, 2008Date of Patent: July 13, 2010Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Publication number: 20080238477Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: ApplicationFiled: February 25, 2008Publication date: October 2, 2008Applicant: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 7426665Abstract: A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks, defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks, determining an expected logic result for a selected logical combination of the individual test inputs, applying the individual test inputs to the first end of each of the at least two of the first sets of tracks, performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result, and flagging an error if the actual result is not identical with the expected logic result.Type: GrantFiled: January 30, 2002Date of Patent: September 16, 2008Assignee: Actel CorporationInventors: Jung-Cheun Lien, Chung-Yuan Sun, Tong Liu, Zili Zhang, Sheng Feng, Eddy C. Huang, Naihui Liao
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Publication number: 20080197878Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: ApplicationFiled: April 29, 2008Publication date: August 21, 2008Applicant: ACTEL CORPORATIONInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 7382155Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: August 10, 2004Date of Patent: June 3, 2008Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 7342416Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: GrantFiled: November 20, 2006Date of Patent: March 11, 2008Assignee: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Publication number: 20070174803Abstract: A method for concurrent search and select of routing patterns for a routing system is provided. The provided method introduces a metric for indicating the goodness of a routing pattern for guiding the selection of search engine at the route finding stage. Next, the method explores routes based on a plurality of feasible routing track segments that represent the longest continuous span of possible routes on a routing layer. Next, the preferred routing patterns can be selected. After that, the method goes to find one or more routing violations and then avoid the routing violations. Furthermore, the avoidance of the routing violation(s) can be implemented by reducing the length of the feasible routing track segment, or removing portion of a routed segment running in parallel and adjacent track(s) of the feasible routing track segment.Type: ApplicationFiled: January 10, 2007Publication date: July 26, 2007Inventors: Jung-Cheun Lien, Minchen Zhao
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Publication number: 20070130094Abstract: The invention details apparatus for rapid calculation of models for routing patterns. The calculation comprises learning or self-adapting mechanisms to gradually improve its accuracy. The outputs from such calculation can be used by a routing system to select routing patterns to control variations from manufacturing process. Depending on the model selection, the application areas include but not limited to yield, process window, and timing variations.Type: ApplicationFiled: December 5, 2006Publication date: June 7, 2007Inventors: Jung-Cheun Lien, Minchen Zhao
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Publication number: 20070106971Abstract: The invention details methods and apparatus for a routing system or router that includes a model. The model can be in many different forms including but not limited to: resolution enhancement technologies such as OPC; lithography model including but not limited to aerial image; pattern-dependent functions; functions for timing/signal integrity/power; manufacturing process variations; and measured silicon data. In one embodiment, the model can be described as input to the system and the model calculator can interact either with the data structure or the query engine of the detail router or both. The model calculator can accept input as a set of geometry description and produce output to guide the query functions. An example technique called set intersection is disclosed herein to combine multiple models in the system. A preferred embodiment of this invention includes a full chip grid-based router being aware of manufacturability.Type: ApplicationFiled: November 1, 2006Publication date: May 10, 2007Inventors: Jung-Cheun Lien, Minchen Zhao
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Publication number: 20070101303Abstract: A method and apparatus for integrated circuit layout optimization are provided. In the conventional art, the major challenges in building integrated circuits (IC) at sub-wavelength geometries include i) to ensure the design intent is faithfully transferred onto silicon; ii) to ensure the design is manufacturable, or with acceptable yield subject to process variations. The present invention provides the method to process a layout database to optimize or correct or fix layout violations or enhancements. The layout violations are identified through various means such as design rules, recommended rules, timing/signal integrity/power constraints, lithography rules, Resolution Enhancement Technologies (RET) requirements and preferences, and process and manufacturing constraints. Particularly, the method, techniques and procedures of creating software tools of the present invention used to perform the layout violations or enhancements are disclosed.Type: ApplicationFiled: November 1, 2006Publication date: May 3, 2007Inventors: Jung-Cheun Lien, Minchen Zhao
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Publication number: 20070089082Abstract: A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.Type: ApplicationFiled: November 8, 2006Publication date: April 19, 2007Applicant: ACTEL CORPORATIONInventors: Tong Liu, Jung-Cheun Lien, Sheng Feng, Eddy Huang, Chung-Yuan Sun, Naihui Liao, Weidong Xiong
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Publication number: 20070075742Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: ApplicationFiled: November 20, 2006Publication date: April 5, 2007Applicant: ACTEL CORPORATIONInventors: Sheng Feng, Jung-Cheun Lien, Eddy Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 7157938Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.Type: GrantFiled: January 18, 2006Date of Patent: January 2, 2007Assignee: Actel CorporationInventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
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Patent number: 7137095Abstract: A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field programmable gate array and configured to transfer signals from the output ports of other tiles in the field programmable gate array. The first set of conductors include vertical conductors that form intersections horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of horizontal conductors to one of the vertical conductors.Type: GrantFiled: February 15, 2002Date of Patent: November 14, 2006Assignee: Actel CorporationInventors: Tong Liu, Jung-Cheun Lien, Sheng Feng, Eddy C. Huang, Chung-Yuan Sun, Naihui Liao, Weidong Xiong
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Patent number: 7132853Abstract: An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.Type: GrantFiled: April 24, 2006Date of Patent: November 7, 2006Assignee: Actel CorporationInventors: Sheng Feng, Tong Liu, Jung-Cheun Lien
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Publication number: 20060186920Abstract: An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.Type: ApplicationFiled: April 24, 2006Publication date: August 24, 2006Inventors: Sheng Feng, Tong Liu, Jung-Cheun Lien