Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.

Abstract: Disclosed is a wafer level chip scale package and a method for manufacturing the same. The wafer level chip scale package includes a semiconductor die having a first coating layer formed thereon; a redistribution layer formed on the first coating layer and connected to the bond pad; an electronic device placed on the first coating layer; a connection member for electrically connecting the electronic device and the redistribution layer; a conductive post formed on the redistribution layer with a predetermined thickness; a second coating layer for enclosing the first coating layer, the redistribution layer, the electronic device, the connection member, and the conductive post; and a solder ball thermally bonded to the conductive post while protruding to the exterior of the second coating layer. This construction makes it easy to manufacture stacked packages and chip scale packages in a wafer level.