Patents by Inventor Jung Hee Yun
Jung Hee Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11987781Abstract: The present invention relates to a gas collection device and is directed to a gas collection device for collecting a gas which is generated while microorganisms are cultured in a super absorbent polymer product. The gas collection device may comprise a constant temperature chamber having an interior that is configured to be maintained at a set temperature; a culture flask unit located inside the constant temperature chamber and configured to culture a bacteria therein; an adsorption unit located outside the constant temperature chamber and configured to receive a gas inside the culture flask unit; a pump unit connected to a rear end of the adsorption unit and configured to suck the gas inside the culture flask unit into the adsorption unit; and a mass flow controller located outside the constant temperature chamber and configured to control a flow rate of the gas sucked into the adsorption unit.Type: GrantFiled: June 28, 2021Date of Patent: May 21, 2024Assignee: LG Chem, Ltd.Inventors: Eun Byeol Ko, Jung Hye Won, Nak Hee Choi, Ji Seok Lee, Eun Yeong Jin, Hae Sung Yun
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Patent number: 10923021Abstract: An electronic device is provided. The electronic device may include a display, a processor operatively connected with the display and configured to generate external reference time information, a display driver integrated circuit configured to periodically or randomly receive the external reference time information from the processor, wherein the display driver integrated circuit is configured to generate internal time information based on an internal clock, to output a clock image corresponding to the internal time information on the display, and if a time error between the external reference time information and the internal time information occurs during the outputting of the clock image, to output the internal time information, the time error of which is corrected, on the display.Type: GrantFiled: May 18, 2020Date of Patent: February 16, 2021Assignees: Samsung Electronics Co., Ltd., CREPAS Technologies Co., Ltd.Inventors: Jong Kon Bae, Dong Hwy Kim, Sang Woo Kim, Jung Hee Yun, Yo Han Lee, Dong Kyoon Han, Yun Pyo Hong, Hong Kook Lee
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Publication number: 20200279522Abstract: An electronic device is provided. The electronic device may include a display, a processor operatively connected with the display and configured to generate external reference time information, a display driver integrated circuit configured to periodically or randomly receive the external reference time information from the processor, wherein the display driver integrated circuit is configured to generate internal time information based on an internal clock, to output a clock image corresponding to the internal time information on the display, and if a time error between the external reference time information and the internal time information occurs during the outputting of the clock image, to output the internal time information, the time error of which is corrected, on the display.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Jong Kon BAE, Dong Hwy KIM, Sang Woo KIM, Jung Hee YUN, Yo Han LEE, Dong Kyoon HAN, Yun Pyo HONG, Hong Kook LEE
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Publication number: 20180061309Abstract: An electronic device is provided. The electronic device may include a display, a processor operatively connected with the display and configured to generate external reference time information, a display driver integrated circuit configured to periodically or randomly receive the external reference time information from the processor, wherein the display driver integrated circuit is configured to generate internal time information based on an internal clock, to output a clock image corresponding to the internal time information on the display, and if a time error between the external reference time information and the internal time information occurs during the outputting of the clock image, to output the internal time information, the time error of which is corrected, on the display.Type: ApplicationFiled: August 30, 2017Publication date: March 1, 2018Inventors: Jong Kon BAE, Dong Hwy KIM, Sang Woo KIM, Jung Hee YUN, Yo Han LEE, Dong Kyoon HAN, Yun Pyo HONG, Hong Kook LEE
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Publication number: 20160109934Abstract: A display driver circuit can include an input selector circuit configured to receive first display data from a high power processor circuit and configured to operate in a normal mode in which the first display data is provided and in a dormant mode in which no image data is provided to the input selector circuit and configured to receive second display data from a low power processor circuit that is configured provide the second display data when the high power processor circuit is in the dormant mode. A controller circuit, can be coupled to switch the first display data or the second display data through the input selector circuit based on the mode of operation of the high power processor circuit.Type: ApplicationFiled: October 21, 2015Publication date: April 21, 2016Inventors: SOO-YOUNG WOO, YANG-HYO KIM, SUN-YOUNG KIM, CHUL-HO KIM, DO-KYUNG KIM, JUNG-HEE YUN
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Patent number: 8780639Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: GrantFiled: May 8, 2012Date of Patent: July 15, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20140104961Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: May 8, 2012Publication date: April 17, 2014Applicant: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Patent number: 8576630Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: GrantFiled: May 8, 2012Date of Patent: November 5, 2013Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Patent number: 8559228Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: GrantFiled: March 16, 2010Date of Patent: October 15, 2013Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20120257465Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: May 8, 2012Publication date: October 11, 2012Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20100254207Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: March 16, 2010Publication date: October 7, 2010Applicant: SILICON STORAGE TECHNOLOGY, INC.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20090219776Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuant T. Vu
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Patent number: 6195293Abstract: A method of erasing a flash memory according to the present invention includes the steps of: performing a first loop erasing operation so that a source electrode is floated, a program gate electrode is applied with a negative voltage and a drain electrode is supplied with an initial erasing voltage; and performing a second loop erasing operation so that the source electrode is floated, the program gate electrode is applied with the negative voltage and the drain electrode is supplied with a normal erasing voltage higher than the initial erasing voltage.Type: GrantFiled: September 27, 1999Date of Patent: February 27, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jung Hee Yun, Poong Yeub Lee
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Patent number: 5796600Abstract: The present invention relates to the charge pump circuit and, more particularly to the charge pump circuit which can decrease the time period of voltage rise of the charge pump circuit by making the charge pumping voltage outputted from the output stage of the pump circuit section to be satisfactorily supplied to the load section, by making the rate of the gate voltage rise of the voltage drop transistor to be higher than the rate of drain voltage rise.Type: GrantFiled: January 27, 1997Date of Patent: August 18, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Jung Hee Yun