Abstract: Provided are a method and an apparatus for analyzing a malicious code by accurately and rapidly analyzing source code extracted from a set of a plurality of malicious codes, calculating a first degree of complexity of each of a plurality of malicious code binaries, select a root binary initially generated, by using the calculated first degree of complexity, and inferring an evolutionary order of the plurality of malicious code binaries, except for the root binary, based on the calculated first degree of complexity and a degree of distance between the plurality of malicious code binaries.

Abstract: An apparatus for controlling driving of a vehicle and a method therefor are provided.

Abstract: A semiconductor memory apparatus includes an address generation circuit and an operation determination circuit. The address generation circuit generates a refresh target address that corresponds to a word line, among a plurality of word lines, the word line being adjacent to another word line in which row hammering has occurred. The operation determination circuit configured to generate an address matching information by comparing a row hammering address with the refresh target address.

Abstract: A semiconductor memory device includes a plurality of memory blocks including a plurality of word lines; a plurality of sense amplifying circuits, each being shared by adjacent memory blocks among the memory blocks; a refresh counter suitable for generating a counting address, a value of which increases according to a refresh command; an address storing circuit suitable for storing first and second target addresses by sampling an active address at different times; and a control circuit suitable for activating a word line corresponding to one of the counting address and the first target address according to the refresh command, and activating at least one word line corresponding to one or more of the active address and the second target address according to an active command.

Abstract: The present invention relates to a positive electrode material, which includes a positive electrode active material, and a coating layer formed on a surface of the positive electrode active material, wherein the coating layer has a form in which polyimide is dispersed and distributed in an island shape, and a method of preparing the same.

Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits suitable for sequentially storing a sampling address as one of a plurality of latch addresses, and sequentially outputting each of the latch addresses as a target address according to a refresh command; a duplication decision circuit suitable for preventing the sampling address from being stored in the address storing circuits when the sampling address is identical to any of the latch addresses stored in the address storing circuits; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to the refresh command.

Abstract: A positive electrode material for a secondary battery and a method of making the same is disclosed herein. In some embodiments, a positive electrode active material includes a lithium composite transition metal oxide including nickel (Ni), cobalt (Co), and manganese (Mn), wherein the lithium composite transition metal oxide includes 60 mol % or more of the nickel (Ni) among metals excluding lithium, and a coating layer is formed on surfaces of particles of the lithium composite transition metal oxide, wherein the coating layer includes a lithium-polymer compound which is formed by a reaction of a lithium by-product with a polymer.

Abstract: A semiconductor memory device includes a plurality of memory blocks including a plurality of word lines; a plurality of sense amplifying circuits, each being shared by adjacent memory blocks among the memory blocks; a refresh counter suitable for generating a counting address, a value of which increases according to a refresh command; an address storing circuit suitable for storing first and second target addresses by sampling an active address at different times; and a control circuit suitable for activating a word line corresponding to one of the counting address and the first target address according to the refresh command, and activating at least one word line corresponding to one or more of the active address and the second target address according to an active command.

Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits suitable for sequentially storing a sampling address as one of a plurality of latch addresses, and sequentially outputting each of the latch addresses as a target address according to a refresh command; a duplication decision circuit suitable for preventing the sampling address from being stored in the address storing circuits when the sampling address is identical to any of the latch addresses stored in the address storing circuits; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to the refresh command.

Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an ECS command based on a refresh command. During an ECS operation, the ECS control circuit generates an ECS mode signal that is activated based on the ECS command and generates an ECS active command, an ECS read command, and an ECS write command to continue the ECS operation.

Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit is configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or is configured to generate the ECS command by performing a second counting operation based on a periodic signal. The ECS control circuit is configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command. The refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature.

Abstract: Provided are a method and an apparatus for analyzing a malicious code by accurately and rapidly analyzing source code extracted from a set of a plurality of malicious codes, calculating a first degree of complexity of each of a plurality of malicious code binaries, select a root binary initially generated, by using the calculated first degree of complexity, and inferring an evolutionary order of the plurality of malicious code binaries, except for the root binary, based on the calculated first degree of complexity and a degree of distance between the plurality of malicious code binaries.

Abstract: An apparatus for responding to vehicle water splashing includes a processor determining the vehicle water splashing based on image data of a nearby vehicle and determining dangerousness caused by the vehicle water splashing to perform vehicle control and storage storing information determined by the processor and the image data of the nearby vehicle.

Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit is configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or is configured to generate the ECS command by performing a second counting operation based on a periodic signal. The ECS control circuit is configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command. The refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature.

Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an ECS command based on a refresh command. During an ECS operation, the ECS control circuit generates an ECS mode signal that is activated based on the ECS command and generates an ECS active command, an ECS read command, and an ECS write command to continue the ECS operation.

Abstract: A method for preparing a positive electrode active material includes: a step for adding a reaction mixture containing a lithium-raw material and a nickel-manganese-cobalt precursor into a first crucible and performing a first heat treatment at a temperature of 500-800° C. to form a pre-calcinated mixture; a step for extracting the pre-calcinated mixture from the first crucible and pulverizing or classifying the same; and a step for adding the pulverized or classified pre-calcinated mixture into a second crucible and performing a second heat treatment at a temperature of 700-1000° C. under an atmosphere in which an oxygen partial pressure is 20% or less to form a lithium nickel-manganese-cobalt-based positive electrode active material, wherein a volume of the pre-calcinated mixture formed after the first heat treatment is 20-50% with respect to a volume of the reaction mixture added into the first crucible.

Abstract: An apparatus for responding to vehicle water splashing includes a processor determining the vehicle water splashing based on image data of a nearby vehicle and determining dangerousness caused by the vehicle water splashing to perform vehicle control and storage storing information determined by the processor and the image data of the nearby vehicle.

Abstract: A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ECC) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal.

Abstract: A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ECC) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal.

Abstract: A semiconductor integrated circuit device may include a main inverter and a negative bias temperature instability (NBTI) compensating circuit. The main inverter may be configured to receive an input signal. The main inverted may be configured to reverse the input signal. The main inverter may include a PMOS transistor and an NMOS transistor. The NBTI compensating circuit may be configured to receive the input signal. The NBTI compensating circuit may be selectively driven in an operation start time section of the PMOS transistor in the main inverter to compensate a driving force of the PMOS transistor.