Abstract: A method of operating a semiconductor device includes performing a pre-sensing operation on selected memory cells; and performing a main sensing operation on the selected memory cells. The performing of the main sensing operation includes selectively precharging first sensing nodes of a plurality of page buffers respectively corresponding to the selected memory cells, based on a result of the pre-sensing operation.

Abstract: A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.

Abstract: A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.

Abstract: A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.

Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

Abstract: Circuits for generating multiple clocks for computer systems are disclosed. One such system includes a circuit configured to generate a core clock, a system bus clock, and a peripheral clock. The frequency of one of the clocks can be reduced or altered without altering the frequencies at which the other clocks oscillate. Also disclosed are methods for incorporating or utilizing the disclosed circuits.

Abstract: Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the flip-flop has a reset terminal and two latches. The method further comprises modifying the layout of the flip-flop to create a clock gating circuit.

Abstract: Circuits for generating multiple clocks for computer systems are disclosed. One such system includes a circuit configured to generate a core clock, a system bus clock, and a peripheral clock. The frequency of one of the clocks can be reduced or altered without altering the frequencies at which the other clocks oscillate. Also disclosed are methods for incorporating or utilizing the disclosed circuits.

Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

Abstract: Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the flip-flop has a reset terminal and two latches. The method further comprises modifying the layout of the flip-flop to create a clock gating circuit.