Abstract: Provided herein are systems, methods and compositions for the use of ultrasound for detection of cells and nanoparticles.

Abstract: A computer system, including a data storage unit which stores first operating system data of the computer system therein; a main memory to which the first operating system data is copied; a data transmission unit which transmits data between the data storage unit and the main memory; and a controller which performs a power-on self test (POST) of the computer system, and controls the data transmission unit to copy the first operating system data stored in the data storage unit to the main memory during the POST.

Abstract: A CMOS image sensor includes an image transfer transistor therein. This image transfer transistor includes a semiconductor channel region of first conductivity type and an electrically conductive gate on the semiconductor channel region. A gate insulating region is also provided. The gate insulating region extends between the semiconductor channel region and the electrically conductive gate. The gate insulating region includes a nitridated insulating layer extending to an interface with the electrically conductive gate and a substantially nitrogen-free insulating layer extending to an interface with the semiconductor channel region. The nitridated insulating layer may be a silicon oxynitride (SiON) layer.

Abstract: A novel contrast mechanism for diagnosing diseased tissue using Ultrasound, Doppler Ultrasonography, Optical Coherence Tomography, or optical Doppler tomography coupled with an externally applied temporally oscillating high-strength magnetic field.

Abstract: The present invention relates to a rotating catheter tip for optical coherence tomography based on the use of an optical fiber that does not rotate, that is enclosed in a catheter, which has a tip rotates under the influence of a fluid drive system to redirect light from the fiber to a surrounding vessel and the light reflected or backscattered from the vessel back to the optical fiber.

Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

Abstract: An apparatus to output multimedia data and a method of outputting the same, more particularly, an apparatus to output multimedia data and a method of outputting the same, in which multimedia data of all applicable formats is converted into multimedia data formats supported by a media center extender so as to be outputted, the apparatus to output multimedia data including a data processing unit receiving video data and audio data, a control unit converting process paths of the video data and the audio data, an encoding unit encoding the video data and the audio data transmitted according to the converted process paths into a predetermined compression format, and a communication unit transmitting the multimedia data according to the encoded result.

Abstract: A method of and an apparatus for providing an application with a remotely controllable interface. An application is displayed in a first mode, in which the user interface is controllable using a mouse or a keyboard. Predetermined data specifying an appearance of the application is collected, the predetermined data are modified to display the application in a second mode, in which the user interface is controllable with a remote control, and the modified data are stored.

Abstract: A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to the presence of impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

Abstract: Provided herein are systems and methods for the detection of cells and compositions using optical coherence tomography.

Abstract: A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySi1-xGex layer stacked on the metallic layer. Methods of forming these capacitors also are provided.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device may include a layered structure and a plug. The layered structure may have a lower insulation layer pattern, a single crystalline silicon pattern, and an upper insulation layer pattern provided on a substrate. A contact hole may be provided in the layered structure. The contact hole may expose the single crystalline silicon pattern and the substrate. The plug may include silicon germanium. The plug may be provided in the contact hole and may be electrically connected to the substrate and the single crystalline silicon pattern.

Abstract: A catheter imaging probe for a patient. The probe includes a conduit through with energy is transmitted. The probe includes a first portion through which the conduit extends. The probe includes a second portion which rotates relative to the conduit to redirect the energy from the conduit. A method for imaging a patient. The method includes the steps of inserting a catheter into the patient. There is the step of rotating a second portion of the catheter relative to a conduit extending through a first portion of the catheter, which redirects the energy transmitted through the conduit to the patient and receives the energy reflected back to the second portion from the patient and redirects the reflected energy to the conduit.

Abstract: In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.

Abstract: In a method of manufacturing a capacitor including a hemispherical grain (HSG) silicon layer, after forming a storage electrode electrically coupled to a contact region of a substrate, the HSG silicon layer is formed on the storage electrode by providing a first gas including silicon and a second gas onto a surface of the storage electrode with a volume ratio of about 1.0:0.1 to about 1.0:5.0. A dielectric layer and a plate electrode are sequentially formed on the HSG silicon layer. A grain size of the HSG silicon layer may be easily adjusted and abnormal growths of the HSG at a lower portion of the storage electrode may be suppressed. Therefore, the HSG silicon layer may be uniformly formed on the storage electrode, and a structural stability of the storage electrode may be improved to prevent electrical defects of the capacitor.

Abstract: A method for forming a capacitor comprises forming a supporting insulating film, an etching stopper film made of alumina series or hafnium oxide series, and a mold insulating film on a surface of a semiconductor substrate having a first structure including conductive plugs surrounded by a first insulating film, patterning the mold insulating film, the etching stopper film and the supporting insulating film to form openings that expose the conductive plugs, forming a storage node conductive film electrically connected to the conductive plugs on the surface of the semiconductor substrate having the openings formed therein and concurrently annealing the etching stopper film, separating the storage node conductive film to form a plurality of storage nodes, exposing at least a part of an outer surface of the storage node by selectively etching remaining mold insulating film, which is exposed by the separated storage node conductive film, until the etching stopper film is exposed, and forming a plurality of plate n

Abstract: An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug.

Abstract: A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySi1-xGex layer stacked on the metallic layer. Methods of forming these capacitors also are provided.

Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.