Abstract: Disclosed is fucosyllactose having antiviral activity and inhibitory activity against viral infection, and a method for preventing or treating a viral infection by administering a composition including fucosyllactose as an active ingredient to a subject in need thereof. It was found that 2?-fucosyllactose and 3-fucosyllactose, which are human milk oligosaccharides (HMOs), have antiviral activity, and in particular, 3-fucosyllactose in vitro and in vivo exhibits much higher antiviral activity and inhibitory activity against viral infection compared to 2?-fucosyllactose and is thus useful as an antiviral agent.

Abstract: A camera module includes a housing, a movable body configured to move in a direction of an optical axis of the housing; a reinforcing member formed integrally on one surface of the movable body, and configured to increase a rigidity of the movable body; and a first buffer member formed in the reinforcing member, and configured to reduce an impactive force between the housing and the movable body.

Abstract: A variable resistive memory device includes a memory cell array and a control circuit block. The memory cell array includes a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block is positioned on at least one of edge portions of the memory cell array. The memory cell array is classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells that are remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block includes a write control unit that generates a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group.

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: A nonvolatile memory apparatus may include a write circuit and a sense amplifier. The write circuit may perform a preselection operation on a selected memory cell. When the selected memory cell was snapped back, the write circuit may selectively perform a reset write operation and a set write operation on the selected memory cell according to write data. When the selected memory cell is not snapped back, the write circuit may apply no voltage and no current to the selected memory cell. The sense amplifier may sense whether the selected memory cell was snapped back.

Abstract: A variable resistive memory device includes a memory cell array and a control circuit block. The memory cell array includes a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block is positioned on at least one of edge portions of the memory cell array. The memory cell array is classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells that are remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block includes a write control unit that generates a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group.

Abstract: A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: A nonvolatile memory apparatus may include a write circuit and a sense amplifier. The write circuit may perform a preselection operation on a selected memory cell. When the selected memory cell was snapped back, the write circuit may selectively perform a reset write operation and a set write operation on the selected memory cell according to write data. When the selected memory cell is not snapped back, the write circuit may apply no voltage and no current to the selected memory cell. The sense amplifier may sense whether the selected memory cell was snapped back.

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.

Abstract: A phase change memory device may be provided. The phase change memory device may include a plurality of Mats, a row control block and a column control block. The row control block may be provided to each of the Mats to control word lines. The column control block may be provided to each of the Mats to control bit lines. When a near phase change memory cell adjacent to the row control block and the column control block is selected, the phase change memory cells located at different positions, which may be spaced apart from the near phase change memory cell, in the Mats except for a reference Mat may be selected.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a write circuit, a first selection circuit, a memory cell, a coupling control circuit, and a coupling circuit. The write circuit may generate a write current corresponding to write data based on a control code signal. The first selection circuit may couple the write circuit to a first line based on a first selection signal, and may allow cell current corresponding to the write current to flow to the first line. The memory cell may be coupled between the first line and a second line, and may store the write data based on the cell current. The coupling control circuit may generate a coupling code signal corresponding to the write current based on the control code signal. The coupling circuit may selectively couple one or more voltage terminals among a plurality of voltage terminals to the second line based on a coupling code signal.

Abstract: An electronic device including a semiconductor memory may be provided. The semiconductor memory may include a write circuit configured for generating a first current. The semiconductor memory may include a first selection circuit configured for coupling the first write circuit to a first line based on a first selection signal. The semiconductor memory may include a second write circuit configured for generating a second current. The semiconductor memory may include a second selection circuit configured for coupling the second write circuit to a second line based on a second selection signal. The semiconductor memory may include a memory cell coupled between the first line and the second line. The semiconductor memory may include a voltage control circuit configured for controlling a voltage level of the second line.

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: A phase change memory device may be provided. The phase change memory device may include a plurality of Mats, a row control block and a column control block. The row control block may be provided to each of the Mats to control word lines. The column control block may be provided to each of the Mats to control bit lines. When a near phase change memory cell adjacent to the row control block and the column control block is selected, the phase change memory cells located at different positions, which may be spaced apart from the near phase change memory cell, in the Mats except for a reference Mat may be selected.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Abstract: A phase change memory device may be provided. The phase change memory device may include a plurality of Mats, a row control block and a column control block. The row control block may be provided to each of the Mats to control word lines. The column control block may be provided to each of the Mats to control bit lines. When a near phase change memory cell adjacent to the row control block and the column control block is selected, the phase change memory cells located at different positions, which may be spaced apart from the near phase change memory cell, in the Mats except for a reference Mat may be selected.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.