Patents by Inventor Jung-Hyun Kwon

Jung-Hyun Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system including memory device and memory controller, and operation method thereof
    Patent number: 10607694
    Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Won-Gyu Shin, Jung-Hyun Kwon, Do-Sun Hong
  • NONVOLATILE MEMORY DEVICE FOR INVALIDATING DATA STORED THEREIN, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF
    Publication number: 20200090746
    Abstract: A memory device includes a plurality of word lines and a plurality of bit lines intersecting the word lines, a memory cell array comprising a plurality of memory cells coupled between the word lines and the bit lines at intersections between the word lines and the bit lines, respectively, an address decoder suitable for decoding an address to access a memory cell selected among the memory cells, and a controller suitable for writing and reading data to and from the selected memory cell by applying voltages to the word lines and bit lines, wherein the controller invalidates data stored in memory cells coupled to a target word line among the word lines by applying an invalidation voltage to the target word line for a set time.
    Type: Application
    Filed: December 26, 2018
    Publication date: March 19, 2020
    Inventors: Jung-Hyun KWON, Jae-Min JANG, Sang-Gu JO
  • MEMORY SYSTEMS FOR MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY SYSTEMS
    Publication number: 20200051627
    Abstract: A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.
    Type: Application
    Filed: December 28, 2018
    Publication date: February 13, 2020
    Applicant: SK hynix Inc.
    Inventors: Do-Sun HONG, Jung Hyun KWON, Won Gyu SHIN, Seung Gyu JEONG
  • Memory system
    Patent number: 10559354
    Abstract: A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Jung-Hyun Kwon, Do-Sun Hong, Won-Gyu Shin
  • CACHE MEMORY, MEMORY SYSTEM INCLUDING THE SAME, AND EVICTION METHOD OF CACHE MEMORY
    Publication number: 20200026664
    Abstract: In a cache memory used for communication between a host and a memory, the cache memory may include a plurality of cache sets, each comprising: a valid bit; N dirty bits; a tag; and N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to a data chunk size of the host, wherein a data chunk size of the memory is N times as large as the data chunk size of the host, where N is an integer greater than or equal to 2.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 23, 2020
    Inventors: Seung-Gyu JEONG, Dong-Gun KIM, Jung-Hyun KWON, Young-Suk MOON
  • Display device having a color conversion layer
    Patent number: 10539826
    Abstract: A display device includes: a first substrate; a second substrate facing the first substrate; a light-amount adjusting layer interposed between the first substrate and the second substrate; and a backlight unit disposed under the first substrate, wherein the second substrate includes a plurality of color conversion layers respectively disposed on a plurality of pixel regions, the color conversion layer includes a partition wall; and a phosphor disposed on areas defined by the partition wall, and the color conversion layer includes an air layer between the second substrate and the phosphor.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: January 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang Keun Lee, Jung Hyun Kwon, Seon Tae Yoon, Hae Il Park
  • Memory system having resistive memory device for scheduling write command and operating method thereof
    Patent number: 10529421
    Abstract: A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Jung-Hyun Kwon, Do-Sun Hong, Won-Gyu Shin
  • MEMORY DEVICE, OPERATING METHOD THEREOF, AND OPERATING METHOD OF MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20200005842
    Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Inventors: Sang-Gu JO, Sung-Eun LEE, Jung-Hyun KWON
  • Memory device, operating method thereof, and operating method of memory system including the same
    Patent number: 10515675
    Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Gu Jo, Sung-Eun Lee, Jung-Hyun Kwon
  • MEMORY SYSTEMS PERFORMING RECONFIGURABLE ERROR CORRECTION OPERATION USING ECC ENGINE WITH FIXED ERROR CORRECTION CAPABILITY
    Publication number: 20190385693
    Abstract: A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.
    Type: Application
    Filed: November 28, 2018
    Publication date: December 19, 2019
    Inventors: Wongyu Shin, Jung Hyun Kwon, Seunggyu Jeong, Do Sun Hong
  • Memory system having resistive memory device and operating method thereof
    Patent number: 10482961
    Abstract: A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Jung-Hyun Kwon, Do-Sun Hong, Won-Gyu Shin
  • Memory controller, memory system including the same and operation method of memory controller
    Patent number: 10474376
    Abstract: An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventors: Jing-Zhe Xu, Jung-Hyun Kwon, Sung-Eun Lee, Jae-Sun Lee, Sang-Gu Jo
  • MEMORY SYSTEM INCLUDING RESISTIVE VARIABLE MEMORY DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20190332322
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of cell regions. The memory controller controls an operation of the memory device. The memory controller includes a random access memory (RAM) and a cell region management unit. The RAM stores an address mapping table. The address mapping table includes physical block addresses for the plurality of cell regions, logical block addresses mapped with the physical block addresses, and status values corresponding to the physical block addresses. The cell region management unit determines whether there is a first cell region to be cleared among the plurality of cell regions, based on the status values, generates a cell clear command when there is the first cell region, and transmits the cell clear command to the memory device.
    Type: Application
    Filed: November 14, 2018
    Publication date: October 31, 2019
    Inventors: Jung Hyun KWON, Seung Gyu JEONG, Won Gyu SHIN, Do-Sun HONG
  • Apparatuses and methods of distributing addresses in memory devices for mitigating write disturbance
    Patent number: 10438655
    Abstract: An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Jung Hyun Kwon, Yong Ju Kim, Do Sun Hong
  • SEMICONDUCTOR MEMORY SYSTEM AND METHOD OF REPAIRING THE SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20190303253
    Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.
    Type: Application
    Filed: December 6, 2018
    Publication date: October 3, 2019
    Applicant: SK hynix Inc.
    Inventors: Wongyu SHIN, Jung Hyun KWON, Seunggyu JEONG, Do Sun HONG
  • MEMORY SYSTEM AND OPERATING METHOD THEREOF
    Publication number: 20190278706
    Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.
    Type: Application
    Filed: October 24, 2018
    Publication date: September 12, 2019
    Inventors: Do-Sun HONG, Jung Hyun KWON, Won Gyu SHIN, Seung Gyu JEONG
  • READ TIME-OUT MANAGERS AND MEMORY SYSTEMS INCLUDING THE READ TIME-OUT MANAGERS
    Publication number: 20190267055
    Abstract: A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.
    Type: Application
    Filed: December 5, 2018
    Publication date: August 29, 2019
    Applicant: SK hynix Inc.
    Inventors: Seunggyu JEONG, Jung Hyun KWON, Wongyu SHIN, Do Sun HONG
  • Wireless Battery Management System And Battery Pack Including Same
    Publication number: 20190260097
    Abstract: A wireless battery management system and a battery pack including the same. The wireless battery management system includes a plurality of slave BMSs coupled to a plurality of battery modules installed one-to-one correspondence, and a master BMS configured to wirelessly transmit a trigger signal to the plurality of slave BMSs, the trigger signal being for ID allocation to the plurality of slave BMSs. Each slave BMS is configured to generate a response signal including a temporary ID in response to the trigger signal, each slave BMS having a different temporary ID, and wirelessly transmit the response signal to the master BMS. The master BMS is configured to receive the response signal from each of the plurality of slave BMSs, and determine formal IDs to be allocated to each slave BMS based on a received signal strength of the response signal from the given slave BMS.
    Type: Application
    Filed: June 14, 2018
    Publication date: August 22, 2019
    Applicant: LG Chem, Ltd.
    Inventors: Jung-Hyun Kwon, Chan-Ha Park, Sang-Hoon Lee, Yean-Sik Choi
  • MEMORY SYSTEM AND OPERATING METHOD THEREOF
    Publication number: 20190237150
    Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.
    Type: Application
    Filed: September 7, 2018
    Publication date: August 1, 2019
    Inventors: Seung-Gyu JEONG, Jung-Hyun KWON, Do-Sun HONG, Won-Gyu SHIN
  • Nonvolatile memory device and operating method thereof
    Patent number: 10359950
    Abstract: A memory device may include a memory cell array having a plurality of memory cells, and a controller suitable for reading data of a memory cell corresponding to an address of write data, among the memory cells, and comparing the write data and the read data to check specific bits different from corresponding bits of the read data, among a plurality of bits of the write data, according to a write operation request. The controller may output a check result to outside after a preset time from the write operation request.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyun Kwon, Sang-Gu Jo, Sung-Eun Lee