Abstract: A sensor cleaning apparatus for a vehicle includes: a sensor housing in which a driver and a sensor are mounted, a cover part configured to rotate and exposed to the outside of the sensor housing through an open region formed on a front surface of the sensor housing, and a blade part connected to the cover part. The blade is rotated as the driver is driven and provided to allow air generated by its rotation to flow toward a front surface and a rear surface of the cover.

Abstract: An apparatus for manufacturing the secondary battery includes a first measurement part photographing unit cells, which are continuously transferred, to measure a position of a first electrode having a relatively large size of the first electrode and a second electrode, which are provided in the unit cells and have polarities opposite to each other, from an image of each of the photographed unit cells; and a first arrangement part disposing the unit cell passing through the first measurement part at a preset position of the separation sheet to adjust an interval between the unit cells disposed on the separation sheet on the basis of the position of the first electrode, which is measured by the first measurement part.

Abstract: A molding apparatus for fabricating a semiconductor package includes an upper mold including an upper cavity, a first side cavity at a first side of the upper cavity, a second side cavity formed at an opposite second side of the upper cavity, and a first driving part connected to the first side cavity and configured to move the first side cavity in a first direction, and a bottom mold including a bottom cavity configured to receive a molding target including a package substrate and at least one semiconductor chip. A width in the first direction between the first side cavity and the second side cavity may be smaller than a width of the package substrate in the first direction and greater than a width in the first direction between a first boundary and a second boundary of the at least one semiconductor chip.

Abstract: In a driving system, first and second inverters are connected to a driving motor, one end of a stator winding through which 3-phase current flows is connected to an output line of the first inverter, and the other end of the stator winding is connected to an output line of the second inverter. A winding pattern of the driving motor includes: coils wound in slots defined in the stator and to which 3-phase current is applied; coils wound on innermost and outermost sides based on a direction toward a rotating shaft of the driving motor in the slots, and being energized by different AC phases; and coils disposed between a first coil located on the outermost side and a second coil located on the innermost side, and being energized by the same AC phases as those of the first and second coils.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.