Patents by Inventor Jung-Mi KO
Jung-Mi KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137821Abstract: Disclosed is a technique for switching from a master node to a secondary node in a communication system. A method of a first communication node may comprise: adding the first communication node as a primary secondary cell (PSCell) to a second communication node through dual connectivity (DC); generating a first user plane path for smart dynamic switching (SDS) and a first instance for supporting the first user plane path according to a request from the second communication node; transmitting information on the first user plane path and the first instance to a terminal; receiving user data based on the first user plane path from the terminal as the first instance; and transmitting the user data to a core network using the first user plane path.Type: ApplicationFiled: October 22, 2023Publication date: April 25, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Soon Gi PARK, Young-Jo KO, IL GYU KIM, Jung Im KIM, Jun Sik KIM, Sung Cheol CHANG, Sun Mi JUN, Yong Seouk CHOI
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Publication number: 20240117389Abstract: The present disclosure is to provide a method capable of producing an organic acid in high yield from an acetic acid strain using synthesis gas as a substrate. According to the present disclosure, the productivity of metabolites with C2 to C6 carbon atoms derived from synthesis gas and the selectivity of hexanoic acid production among metabolites can be improved through a first fermentation step of simultaneously providing a substrate comprising synthesis gas and sugar; and a second fermentation step of semi-mixotrophic fermentation of providing only the substrate comprising the synthesis gas. Therefore, the disclosure can contribute to sustainable chemical production using synthesis gas.Type: ApplicationFiled: September 19, 2023Publication date: April 11, 2024Inventors: Youngsoon UM, Deurim YUN, Sun Mi LEE, Gyeongtaek GONG, Ja Kyong KO, Jung Ho AHN
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Patent number: 11636898Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: GrantFiled: June 3, 2021Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventors: Jung Mi Ko, Kwang Ho Baek, Seong Je Park, Young Don Jung, Ji Hwan Kim, Jung Hwan Lee
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Patent number: 11152072Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of first even page buffers suitable for reading data from first even-numbered memory cells among the plurality of memory cells, and storing the read data, a plurality of first odd page buffers suitable for reading data from first odd-numbered memory cells among the plurality of memory cells, and storing the read data, and a plurality of first cache buffers corresponding to the first even page buffers, suitable for storing data received through a first common node from the first even page buffers, and a plurality of second cache buffers corresponding to the first odd page buffers, and suitable for storing data received through the first common node from the first odd page buffers.Type: GrantFiled: October 24, 2019Date of Patent: October 19, 2021Assignee: SK hynix Inc.Inventors: Jung-Mi Ko, Ji-Hwan Kim, Seong-Je Park
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Publication number: 20210287749Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Jung Mi KO, Kwang Ho BAEK, Seong Je PARK, Young Don JUNG, Ji Hwan KIM, Jung Hwan LEE
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Publication number: 20210280254Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: ApplicationFiled: May 12, 2021Publication date: September 9, 2021Inventors: Jung Mi KO, Kwang Ho BAEK, Seong Je PARK, Young Don JUNG, Ji Hwan KIM, Jung Hwan LEE
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Patent number: 11107541Abstract: The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.Type: GrantFiled: May 13, 2020Date of Patent: August 31, 2021Assignee: SK hynix Inc.Inventors: Young Don Jung, Jung Mi Ko, Kwang Ho Baek, Chang Han Son, Jung Hwan Lee
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Patent number: 11037629Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: GrantFiled: December 27, 2019Date of Patent: June 15, 2021Assignee: SK hynix Inc.Inventors: Jung Mi Ko, Kwang Ho Baek, Seong Je Park, Young Don Jung, Ji Hwan Kim, Jung Hwan Lee
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Publication number: 20210166771Abstract: The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.Type: ApplicationFiled: May 13, 2020Publication date: June 3, 2021Applicant: SK hynix Inc.Inventors: Young Don JUNG, Jung Mi KO, Kwang Ho BAEK, Chang Han SON, Jung Hwan LEE
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Patent number: 10998053Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.Type: GrantFiled: November 6, 2019Date of Patent: May 4, 2021Assignee: SK hynix Inc.Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
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Patent number: 10971234Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.Type: GrantFiled: October 31, 2019Date of Patent: April 6, 2021Assignee: SK hynix Inc.Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
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Patent number: 10937513Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.Type: GrantFiled: October 29, 2019Date of Patent: March 2, 2021Assignee: SK hynix Inc.Inventors: Jung Mi Ko, Kwang Ho Baek, Ji Hwan Kim, Seong Je Park, Sung Hoon Ahn, Young Don Jung
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Publication number: 20200381055Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: ApplicationFiled: December 27, 2019Publication date: December 3, 2020Inventors: Jung Mi KO, Kwang Ho BAEK, Seong Je PARK, Young Don JUNG, Ji Hwan KIM, Jung Hwan LEE
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Publication number: 20200321058Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.Type: ApplicationFiled: October 31, 2019Publication date: October 8, 2020Applicant: SK hynix Inc.Inventors: Jung Hwan LEE, Jung Mi KO, Ji Hwan KIM, Kwang Ho BAEK, Young Don JUNG
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Publication number: 20200321042Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.Type: ApplicationFiled: November 6, 2019Publication date: October 8, 2020Applicant: SK hynix Inc.Inventors: Jung Hwan LEE, Jung Mi KO, Ji Hwan KIM, Kwang Ho BAEK, Young Don JUNG
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Publication number: 20200202963Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.Type: ApplicationFiled: October 29, 2019Publication date: June 25, 2020Applicant: SK hynix Inc.Inventors: Jung Mi KO, Kwang Ho BAEK, Ji Hwan KIM, Seong Je PARK, Sung Hoon AHN, Young Don JUNG
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Publication number: 20200135282Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of first even page buffers suitable for reading data from first even-numbered memory cells among the plurality of memory cells, and storing the read data, a plurality of first odd page buffers suitable for reading data from first odd-numbered memory cells among the plurality of memory cells, and storing the read data, and a plurality of first cache buffers corresponding to the first even page buffers, suitable for storing data received through a first common node from the first even page buffers, and a plurality of second cache buffers corresponding to the first odd page buffers, and suitable for storing data received through the first common node from the first odd page buffers.Type: ApplicationFiled: October 24, 2019Publication date: April 30, 2020Inventors: Jung-Mi KO, Ji-Hwan KIM, Seong-Je PARK