Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data. Further, the semiconductor memory apparatus may also include an enable signal generation block configured to generate a write driver enable signal and a sense amplifier enable signal according to a comparison result of the input data and the output data.

Abstract: A semiconductor memory apparatus may include a program voltage generation block configured to generate a program voltage in response to program codes; a precharge voltage generation block configured to generate a precharge voltage in response to the program codes and addresses; and a main bit line configured to be applied with the program voltage and the precharge voltage.

Abstract: A semiconductor memory apparatus may include a program voltage generation block configured to generate a program voltage in response to program codes; a precharge voltage generation block configured to generate a precharge voltage in response to the program codes and addresses; and a main bit line configured to be applied with the program voltage and the precharge voltage.

Abstract: A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data. Further, the semiconductor memory apparatus may also include an enable signal generation block configured to generate a write driver enable signal and a sense amplifier enable signal according to a comparison result of the input data and the output data.

Abstract: A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal.

Abstract: A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode.

Abstract: A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal.

Abstract: A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.

Abstract: A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode.

Abstract: A block control command generation circuit includes first and second latch units, an input selection unit, a pull-down driving unit, and an output selection unit. The first and second latch units store initial values at different levels in response to initialization signals. The input selection unit selectively transmits a first block control signal to the first latch unit in response to an input enable signal. The pull-down driving unit selectively pull-down drives an input node of the second latch unit in response to a second block control signal and the input enable signal. The output selection unit outputs signals, which are stored in the first and second latch units, as first and second block control command signals in response to an output enable signal, respectively.

Abstract: A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.

Abstract: A block control command generation circuit includes first and second latch units, an input selection unit, a pull-down driving unit, and an output selection unit. The first and second latch units store initial values at different levels in response to initialization signals. The input selection unit selectively transmits a first block control signal to the first latch unit in response to an input enable signal. The pull-down driving unit selectively pull-down drives an input node of the second latch unit in response to a second block control signal and the input enable signal. The output selection unit outputs signals, which are stored in the first and second latch units, as first and second block control command signals in response to an output enable signal, respectively.