Patents by Inventor Jung-Pang Huang
Jung-Pang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10049955Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.Type: GrantFiled: April 26, 2017Date of Patent: August 14, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Patent number: 9899237Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.Type: GrantFiled: February 7, 2014Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Patent number: 9812340Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: GrantFiled: March 18, 2016Date of Patent: November 7, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Publication number: 20170229364Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.Type: ApplicationFiled: April 26, 2017Publication date: August 10, 2017Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Publication number: 20160196990Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: ApplicationFiled: March 18, 2016Publication date: July 7, 2016Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Patent number: 9324585Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: GrantFiled: October 18, 2012Date of Patent: April 26, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Publication number: 20160079110Abstract: A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes.Type: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Inventors: Kuan-Wei Chuang, Shih-Kuang Chiu, Chun-Tang Lin, Jung-Pang Huang
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Patent number: 9117698Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.Type: GrantFiled: August 1, 2014Date of Patent: August 25, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Jung-Pang Huang, Hsin-Yi Liao, Shih-Kuang Chiu, Guang-Hwa Ma
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Patent number: 8895367Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: GrantFiled: August 12, 2013Date of Patent: November 25, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Publication number: 20140342507Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.Type: ApplicationFiled: August 1, 2014Publication date: November 20, 2014Inventors: Yan-Heng Chen, Jung-Pang Huang, Hsin-Yi Liao, Shih-Kuang Chiu, Guang-Hwa Ma
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Patent number: 8829672Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.Type: GrantFiled: July 31, 2012Date of Patent: September 9, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Jung-Pang Huang, Hsin-Yi Liao, Shih-Kuang Chiu, Guang-Hwa Ma
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Publication number: 20140183721Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved.Type: ApplicationFiled: March 18, 2013Publication date: July 3, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yan-Heng Chen, Chiang-Cheng Chang, Jung-Pang Huang, Hsi-Chang Hsu, Yan-Yi Liao
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Publication number: 20140154842Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.Type: ApplicationFiled: February 7, 2014Publication date: June 5, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Publication number: 20140134797Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.Type: ApplicationFiled: August 29, 2013Publication date: May 15, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chieh-Yuan Chi, Jung-Pang Huang, Yan-Heng Chen, Hsi-Chang Hsu, Chiang-Cheng Chang, Shih-Kuang Chiu
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Publication number: 20140117537Abstract: Disclosed is a semiconductor package including an encapsulant having a top surface and a bottom surface opposite to the top surface; a semiconductor chip embedded in the encapsulant having an active surface, an inactive surface opposite to the active surface, and lateral surfaces interconnecting the active surface and the inactive surface, wherein the active surface protrudes from the bottom surface of the encapsulant and the semiconductor chip further has a plurality of electrode pads disposed on the active surface; a positioning member layer formed on a portion of the bottom surface of the encapsulant, covering the lateral surfaces of the semiconductor chip that protrude therefrom, and exposing the active surface; and a build-up trace structure disposed on the active surface of the semiconductor chip and the positioning member layer formed on the bottom surface of the encapsulant. The present invention also provides a method of fabricating a semiconductor package.Type: ApplicationFiled: December 28, 2012Publication date: May 1, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chen-Han Lin, Kuo-Hsiang Li, Jung-Pang Huang, Nan-Jia Huang, Hsin-Yi Liao
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Patent number: 8680692Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.Type: GrantFiled: April 5, 2012Date of Patent: March 25, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Publication number: 20140021629Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: ApplicationFiled: October 18, 2012Publication date: January 23, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Publication number: 20130330883Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: ApplicationFiled: August 12, 2013Publication date: December 12, 2013Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Publication number: 20130256875Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.Type: ApplicationFiled: July 31, 2012Publication date: October 3, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yan-Heng Chen, Jung-Pang Huang, Hsin-Yi Liao, Shih-Kuang Chiu, Guang-Hwa Ma
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Publication number: 20130228915Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.Type: ApplicationFiled: June 27, 2012Publication date: September 5, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu