Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

Abstract: Aspects disclosed in the detailed description include hardware accelerated storage compression. In one aspect, prior to writing an uncompressed data block to the storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data blocks individually into a compressed data block and allocates the compressed data block to a storage data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data blocks. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block.

Abstract: Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

Abstract: Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

Abstract: A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.

Abstract: Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify received differential data and reference input voltages with a smaller sense amplifier offset voltage to provide larger sense margin between different storage states of memory bitcell(s). The OCZS-SA is configured to cancel out offset voltages of input and complement input transistors, and keep the input and complement input transistors in their activated state during sensing phases so that sensing is not performed in their “dead zones” when their gate-to-source voltage (Vgs) is below their respective threshold voltages.

Abstract: In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.

Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.