Patents by Inventor Jung-Pin Huang
Jung-Pin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9754927Abstract: A multi-chip stack structure and a method for fabricating the same are provided.Type: GrantFiled: October 27, 2014Date of Patent: September 5, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chung-Lun Liu, Jung-Pin Huang, Yi-Feng Chang, Chin-Huang Chang
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Patent number: 9058971Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.Type: GrantFiled: May 30, 2013Date of Patent: June 16, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chih-Yuan Shih, Shih-Liang Peng, Jung-Pin Huang, Chin-Yu Ku, Hsien-Wen Chen
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Publication number: 20150044821Abstract: A multi-chip stack structure and a method for fabricating the same are provided.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Inventors: Chung-Lun Liu, Jung-Pin Huang, Yi-Feng Chang, Chin-Huang Chang
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Patent number: 8896130Abstract: A multi-chip stack structure and a method for fabricating the same are provided.Type: GrantFiled: November 7, 2008Date of Patent: November 25, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chung-Lun Liu, Jung-Pin Huang, Yi-Feng Chang, Chin-Huang Chang
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Patent number: 8802507Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.Type: GrantFiled: November 2, 2012Date of Patent: August 12, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
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Publication number: 20140192832Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.Type: ApplicationFiled: May 30, 2013Publication date: July 10, 2014Inventors: Chih-Yuan Shih, Shih-Liang Peng, Jung-Pin Huang, Chin-Yu Ku, Hsien-Wen Chen
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Patent number: 8304891Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.Type: GrantFiled: December 4, 2008Date of Patent: November 6, 2012Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
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Publication number: 20110227226Abstract: The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chiang-Cheng Chiang, Chien-Ping Huang, Chin-Huang Chang, Chi-Hsin Chiu, Jung-Pin Huang
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Patent number: 7981729Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.Type: GrantFiled: June 18, 2010Date of Patent: July 19, 2011Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pin Huang, Chin-Huang Chang, Chien-Ping Huang, Chung-Lun Liu, Cheng-Hsu Hsiao
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Publication number: 20100255635Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.Type: ApplicationFiled: June 18, 2010Publication date: October 7, 2010Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Jung-Pin Huang, Chin-Huang Chang, Chien-Ping Huang, Chung-Lun Liu, Cheng-Hsu Hsiao
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Patent number: 7655503Abstract: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.Type: GrantFiled: January 2, 2007Date of Patent: February 2, 2010Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pin Huang, Chin-Huang Chang, Chung-Lun Liu
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Publication number: 20090294959Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.Type: ApplicationFiled: December 4, 2008Publication date: December 3, 2009Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
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Publication number: 20090140440Abstract: A multi-chip stack structure and a method for fabricating the same are provided.Type: ApplicationFiled: November 7, 2008Publication date: June 4, 2009Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chung-Lun Liu, Jung-Pin Huang, Yi-Feng Chang, Chin-Huang Chang
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Publication number: 20090032928Abstract: The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements.Type: ApplicationFiled: July 30, 2008Publication date: February 5, 2009Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chiang, Chien-Ping Huang, Chin-Huang Chang, Chi-Hsin Chiu, Jung-Pin Huang
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Publication number: 20090014860Abstract: A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.Type: ApplicationFiled: January 29, 2008Publication date: January 15, 2009Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chung-Lun Liu, Jung-Pin Huang, Chin-Huang Chang, Chih-Ming Huang, Cheng-Hsu Hsiao
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Publication number: 20080283994Abstract: A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor packType: ApplicationFiled: May 16, 2008Publication date: November 20, 2008Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Ho-Yi Tsai, Chien-Ping Huang, Jung-Pin Huang, Chin-Huang Chang, Cheng-Hsu Hsiao
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Publication number: 20080224289Abstract: A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires.Type: ApplicationFiled: March 13, 2008Publication date: September 18, 2008Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pin Huang, Chin-Huang Chang, Chien-Ping Huang, Chung-Lun Liu, Cheng-Hsu Hsiao
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Publication number: 20080174030Abstract: The present invention provides a multi-chip stacking structure. The multichip stacking structure comprises: a chip carrier; a first and a second chip modules respectively having a plurality of first and a plurality of second chips, wherein each chips has a bond pad and the chips are stacked on the chip carrier in a step-like manner to expose the bond pads; and a plurality of bonding wires for electrically connecting the bond pads of the first and the second chip modules to the chip carrier, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer having fillers therein to support the bottom chip, and the bottom chip is deviated from the top chip horizontally in a direction toward the bonding wires of the first chip module.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chung-Lun Liu, Chin-Huang Chang, Yi-Feng Chang, Jung-Pin Huang, Chih-Ming Huang
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Publication number: 20080176358Abstract: The present invention provides a fabrication method of a multi-chip stacking structure. The method includes steps of: stacking the first chips on the chip carrier in a step-like manner to form a first chip module; electrically connecting the first chip module to the chip carrier by a plurality of first bonding wires; stacking the second chips on the first chip module in step-like manner to form a second chip module, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer with the bottom chip deviated from the top chip horizontally in a direction toward the first bonding wires; and electrically connecting the bond pads of the second chip module to the chip carrier by a plurality of second bonding wires.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: Silicon Precision Industries Co., Ltd.Inventors: Chung-Lun Liu, Chin-Huang Chang, Yi-Feng Chang, Jung-Pin Huang, Chih-Ming Huang
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Publication number: 20070108571Abstract: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.Type: ApplicationFiled: January 2, 2007Publication date: May 17, 2007Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pin Huang, Chin-Huang Chang, Chung-Lun Liu