Abstract: A method of activating a secondary battery includes an operation of deriving a reduction reaction voltage according to an electrolyte additive, a pre-charging operation of pre-charging the secondary battery into which an electrolyte containing the electrolyte additive is injected, and a pre-aging operation of wetting an electrode assembly accommodated in the secondary battery with the injected electrolyte and aging the electrode assembly. A charging termination voltage in the pre-charging operation is less than the reduction reaction voltage.

Abstract: The present disclosure relates to a serum exosomal SF3B4 marker composition for diagnosing early stage hepatocellular carcinoma for noninvasive in vitro diagnosis, wherein, by analyzing an expression level of SF3B4 in plasma proteins as well as expression of SF3B4 in exosomes present in sera of hepatocellular carcinoma patients, the possibility as the most suitable liquid biopsy marker was identified, and a new noninvasive biomarker with high diagnostic accuracy in early stage hepatocellular carcinoma for which no reliable biomarker exists at this present was discovered. As such, by using exosomes to identify cancer cell genomes and proteomes without biopsy, the exosomes are highly applicable in the future as a diagnostic biomarker that is useful in a disease group with a high risk in the biopsy such as hepatocellular carcinoma.

Abstract: Disclosed are new uses of lactic acid bacteria, in particular Lactobacillus plantarum, for protecting animals from pathogenic bacterial infection, specifically, methods for reducing the mortality rate of animals against infection of pathogenic bacteria, methods for reducing the growth of pathogenic bacteria in the gastrointestinal tract of the animals, as well as methods of increasing and/or stimulating immune system of the animal through the use of such lactic acid bacteria.

Abstract: Disclosed are new uses of lactic acid bacteria, in particular Lactobacillus plantarum, for protecting animals from pathogenic bacterial infection, specifically, methods for reducing the mortality rate of animals against infection of pathogenic bacteria, methods for reducing the growth of pathogenic bacteria in the gastrointestinal tract of the animals, as well as methods of increasing and/or stimulating immune system of the animal through the use of such lactic acid bacteria.

Abstract: A memory device for storing a plurality of macroblocks may include a plurality of memory banks. Each macroblock may include m*n pixel data, wherein m is a positive integer, and wherein n also is a positive integer. The plurality of memory banks is adapted to store the pixel data, and wherein each memory bank is sized to store rows of m pixel data. An image processing system may include: a memory adapted to store a plurality of macroblocks; and a video codec. The memory may include a plurality of memory banks. Each memory bank may be sized to store rows of m pixel data. The video codec may be adapted to encode pixel data read from the memory. The video codec also may be adapted to decode the pixel data read from the memory.

Abstract: According to a coefficient variable length coding method adopting four-stage pipeline, a 3-dimension value including a run, a level and a last data is obtained by performing a run length coding upon coefficient data, where, after transferring the 3-dimension value, a variable bit vector is obtained from the transferred 3-dimension value and the variable length bit vector is stored, and where, particularly in case the pipeline breaks, the method reuses the previously obtained 3-dimension value to minimize process time such that the coefficient variable length coding is swiftly performed by the efficient pipeline operation, and the broken pipeline may be restored within minimized time.

Abstract: Exemplary embodiments of the present invention provide a data processing system which may include a task scheduler for enabling a plurality of independent data processing units to be operable in pipelining streams and/or controlling pipelined operations to be differentiated by tasks, and a memory pool for storing data from the data processing units. The data processing units may perform tasks in response to task start signals provided from the task scheduler. The data processing units may complete the tasks as instructed by the task scheduler, transmit task end signals to the scheduler and transition into standby states.

Abstract: A motion-vector operation device includes an upper memory composed of first and second banks that store motion vectors of a lower block group belonging to a macroblock, a left memory storing motion vectors of a right block group belonging to a macroblock, and an estimator predicting a motion vector of a current block with reference to the motion vectors stored in the first and second banks of the upper memory and the left memory in accordance with an operation mode and a position of the current block in a super macroblock.

Abstract: A motion estimator and an estimation method for a video encoder to reduce power consumption by reducing the computational complexity of the motion estimator. In an upper step, a full search for a ±4 pixel search region for a 4×4 pixel block is performed at ¼ video resolution, to detect two motion vector candidates. In a medium step, a partial search for two vector candidates selected in the upper step and one vector candidate using a spatial correlation is performed for a 8×8 block within a ±1 or ±2 search region, to decide one motion vector candidate. In a lower step, a partial search for the ±1 or ±2 search region on 16×16 block is performed at full resolution, and a half pixel search for a motion vector candidate obtained in the lower step is performed to estimate a final motion vector. A ±4 pixel search region is operatively divided into four search regions, and the estimator sequentially searches the four ±2 pixel search regions to sequentially output SAD values.

Abstract: A camera interface employing a direct memory access (DMA) unit to digitally perform an image transformation such as “flipping” and “rotating” an image (e.g., to correct for X-axis, Y-axis, or XY-axes mirroring). The image transforming DMA unit includes an address generator and a data selector. The address generator appropriately modifies a frame start address, a burst transfer address, a line start address, of an image frame, based on the X, Y, or XY mirrored image mode. The data selector changes the sequences of words and of pixels in a word based upon the mirrored image mode.

Abstract: A motion estimator and an estimation method for a video encoder to reduce power consumption by reducing the computational complexity of the motion estimator. In an upper step, a full search for a ±4 pixel search region for a 4×4 pixel block is performed at ¼ video resolution, to detect two motion vector candidates. In a medium step, a partial search for two vector candidates selected in the upper step and one vector candidate using a spatial correlation is performed for a 8×8 block within a ±1 or ±2 search region, to decide one motion vector candidate. In a lower step, a partial search for the ±1 or ±2 search region on 16×16 block is performed at full resolution, and a half pixel search for a motion vector candidate obtained in the lower step is performed to estimate a final motion vector. A ±4 pixel search region is operatively divided into four search regions, and the estimator sequentially searches the four ±2 pixel search regions to sequentially output SAD values.

Abstract: A memory device for storing a plurality of macroblocks may include a plurality of memory banks. Each macroblock may include m*n pixel data, wherein m is a positive integer, and wherein n also is a positive integer. The plurality of memory banks is adapted to store the pixel data, and wherein each memory bank is sized to store rows of m pixel data. An image processing system may include: a memory adapted to store a plurality of macroblocks; and a video codec. The memory may include a plurality of memory banks. Each memory bank may be sized to store rows of m pixel data. The video codec may be adapted to encode pixel data read from the memory. The video codec also may be adapted to decode the pixel data read from the memory.

Abstract: A motion estimator and an estimation method for a video encoder to reduce power consumption by reducing the computational complexity of the motion estimator. In an upper step, a full search for a ±4 pixel search region for a 4×4 pixel block is performed at ¼ video resolution, to detect two motion vector candidates. In a medium step, a partial search for two vector candidates selected in the upper step and one vector candidate using a spatial correlation is performed for a 8×8 block within a ±1 or ±2 search region, to decide one motion vector candidate. In a lower step, a partial search for the ±1 or ±2 search region on 16×16 block is performed at full resolution, and a half pixel search for a motion vector candidate obtained in the lower step is performed to estimate a final motion vector. A ±4 pixel search region is operatively divided into four search regions, and the estimator sequentially searches the four ±2 pixel search regions to sequentially output SAD values.

Abstract: A context-adaptive variable length coding (VLC) apparatus includes a coefficient information generation unit configured to generate coefficient information used for coding variable-length-code coefficients for a selected block of a selected macroblock of image data that is read out in response to an information generation control signal, a bit data generation unit configured to operate in response to a bit generation control signal, and to code coefficients of a previous block, which is read out just before the selected block, using coefficient information of the previous block, and a control unit configured to generate the information generation control signal and the bit generation control signal, and to cause the coefficient information generation unit and the bit data generation unit to operate at in parallel using the information generation control signal and the bit generation control signal. A method of variable-length coding coefficients of image data is also provided.

Abstract: A motion-vector operation device includes an upper memory composed of first and second banks that store motion vectors of a lower block group belonging to a macroblock, a left memory storing motion vectors of a right block group belonging to a macroblock, and an estimator predicting a motion vector of a current block with reference to the motion vectors stored in the first and second banks of the upper memory and the left memory in accordance with an operation mode and a position of the current block in a super macroblock.

Abstract: A deblocking filter includes a current macroblock buffer memory configured to store video data of a current macroblock to be filtered, a side macroblock buffer memory configured to store a portion of video data of neighboring macroblocks located on the side of the current macroblock, a register buffer array configured to store video data read from the current macroblock buffer memory for current filtering, video data read from the side macroblock buffer memory, and data of neighboring macroblocks, and an edge filter that is connected to the register buffer array and is configured to perform horizontal or vertical filtering on an edge of a subblock of the current macroblock of video data and to perform the other of horizontal or vertical filtering on an edge of a subsequent subblock of the current macroblock of the video data, simultaneously. Vertical filtering uses the data from the neighboring macroblocks and horizontal filtering uses the video data from the side macroblock buffer memory.

Abstract: An apparatus and method for pipelined deblocking includes a filter having a filtering engine, a plurality of registers in signal communication with the filtering engine, a pipeline control unit in signal communication with the filtering engine, and a finite state machine in signal communication with the pipeline control unit; and a method of filtering a block of pixel data processed with block transformations to reduce blocking artifacts includes filtering a first edge of the block, and filtering a third edge of the block no more than three edges after filtering the first edge, wherein the third edge is perpendicular to the first edge.

Abstract: According to a coefficient variable length coding method adopting four-stage pipeline, a 3-dimension value including a run, a level and a last data is obtained by performing a run length coding upon coefficient data, where, after transferring the 3-dimension value, a variable bit vector is obtained from the transferred 3-dimension value and the variable length bit vector is stored, and where, particularly in case the pipeline breaks, the method reuses the previously obtained 3-dimension value to minimize process time such that the coefficient variable length coding is swiftly performed by the efficient pipeline operation, and the broken pipeline may be restored within minimized time.

Abstract: A camera interface employing a direct memory access (DMA) unit to digitally perform an image transformation such as “flipping” and “rotating” an image (e.g., to correct for X-axis, Y-axis, or XY-axes mirroring). The image transforming DMA unit includes an address generator and a data selector. The address generator appropriately modifies a frame start address, a burst transfer address, a line start address, of an image frame, based on the X, Y, or XY mirrored image mode. The data selector changes the sequences of words and of pixels in a word based upon the mirrored image mode.

Abstract: Exemplary embodiments of the present invention provide a data processing system which may include a task scheduler for enabling a plurality of independent data processing units to be operable in pipelining streams and/or controlling pipelined operations to be differentiated by tasks, and a memory pool for storing data from the data processing units. The data processing units may perform tasks in response to task start signals provided from the task scheduler. The data processing units may complete the tasks as instructed by the task scheduler, transmit task end signals to the scheduler and transition into standby states.