Patents by Inventor Jung Tak SEO

Jung Tak SEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Graphene-layered structure, method of preparing the same, and transparent electrode and transistor including graphene-layered structure
    Patent number: 9193133
    Abstract: A method of directly growing graphene of a graphene-layered structure, the method including ion-implanting at least one ion of a nitrogen ion and an oxygen ion on a surface of a silicon carbide (SiC) thin film to form an ion implantation layer in the SiC thin film; and heat treating the SiC thin film with the ion implantation layer formed therein to graphenize a SiC surface layer existing on the ion implantation layer.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeon-jin Shin, Jae-young Choi, Joung-real Ahn, Jung-tak Seo
  • GRAPHENE-LAYERED STRUCTURE, METHOD OF PREPARING THE SAME, AND TRANSPARENT ELECTRODE AND TRANSISTOR INCLUDING GRAPHENE-LAYERED STRUCTURE
    Publication number: 20140141265
    Abstract: A method of directly growing graphene of a graphene-layered structure, the method including ion-implanting at least one ion of a nitrogen ion and an oxygen ion on a surface of a silicon carbide (SiC) thin film to form an ion implantation layer in the SiC thin film; and heat treating the SiC thin film with the ion implantation layer formed therein to graphenize a SiC surface layer existing on the ion implantation layer.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Hyeon-jin SHIN, Jae-young CHOI, Joung-real AHN, Jung-tak SEO
  • Graphene-layered structure, method of preparing the same, and transparent electrode and transistor including graphene-layered structure
    Patent number: 8679951
    Abstract: A method of directly growing graphene of a graphene-layered structure, the method including ion-implanting at least one ion of a nitrogen ion and an oxygen ion on a surface of a silicon carbide (SiC) thin film to form an ion implantation layer in the SiC thin film; and heat treating the SiC thin film with the ion implantation layer formed therein to graphenize a SiC surface layer existing on the ion implantation layer.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-jin Shin, Jae-young Choi, Joung-real Ahn, Jung-tak Seo
  • GRAPHENE-LAYERED STRUCTURE, METHOD OF PREPARING THE SAME, AND TRANSPARENT ELECTRODE AND TRANSISTOR INCLUDING GRAPHENE-LAYERED STRUCTURE
    Publication number: 20120326128
    Abstract: A method of directly growing graphene of a graphene-layered structure, the method including ion-implanting at least one ion of a nitrogen ion and an oxygen ion on a surface of a silicon carbide (SiC) thin film to form an ion implantation layer in the SiC thin film; and heat treating the SiC thin film with the ion implantation layer formed therein to graphenize a SiC surface layer existing on the ion implantation layer.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 27, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeon-jin SHIN, Jae-young CHOI, Joung-real AHN, Jung-tak SEO
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20090108317
    Abstract: A method of fabricating a semiconductor device includes forming a first interlayer insulating film including a storage node contact plug over a semiconductor substrate. A second interlayer insulating film is formed over the first interlayer insulating film and the storage node contact plug. A mask pattern is formed over the second interlayer insulating film to expose a storage node region. The second interlayer insulating film and the first interlayer insulating film is selectively etched to form a recess exposing a portion of the storage node contact plug. A lower storage node is formed in the recess. The storage node includes a concave structure that surrounds the exposed storage node contact plug. A dip-out process is performed to remove the second interlayer insulating film. A dielectric film is formed over the semiconductor substrate including the lower storage node. A plate electrode is deposited over the dielectric film to form a capacitor.
    Type: Application
    Filed: December 28, 2007
    Publication date: April 30, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jung Tak SEO