Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

Abstract: An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.

Abstract: An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.

Abstract: A nitride semiconductor device is provided, including a substrate having a first surface and a second surface opposite to each other; a nucleation layer disposed on the first surface of the substrate; a doped nitride semiconductor layer disposed on the nucleation layer; a doped first buffer layer disposed on the doped nitride semiconductor layer; a channel layer disposed on the doped first buffer layer; a barrier layer disposed on the channel layer; a first electrode disposed on the barrier layer; a second electrode electrically connected to the doped nitride semiconductor layer; and a doped region disposed at least in a portion of the doped nitride semiconductor layer, wherein the doped region is extended from below the first electrode to be partially overlapped with the second electrode.

Abstract: Provided is an enhancement mode HEMT device including a substrate, a channel layer, a first barrier layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The first barrier layer is disposed on the channel layer. At least one trench penetrates through the first barrier layer and extends into the channel layer. The gate is disposed on the first barrier layer, fills in the at least one trench and is in contact with the channel layer. The source and the drain are disposed in the first barrier layer and the channel layer and located at two sides of the gate.

Abstract: A nitride semiconductor device is provided, including a substrate having a first surface and a second surface opposite to each other; a nucleation layer disposed on the first surface of the substrate; a doped nitride semiconductor layer disposed on the nucleation layer; a doped first buffer layer disposed on the doped nitride semiconductor layer; a channel layer disposed on the doped first buffer layer; a barrier layer disposed on the channel layer; a first electrode disposed on the barrier layer; a second electrode electrically connected to the doped nitride semiconductor layer; and a doped region disposed at least in a portion of the doped nitride semiconductor layer, wherein the doped region is extended from below the first electrode to be partially overlapped with the second electrode.

Abstract: A hetero-junction Schottky diode device includes a buffer layer, at least one channel layer, at least one barrier layer and a Schottky metal layer. The buffer layer is disposed on a substrate. The at least one channel layer is disposed on the buffer layer. The at least one barrier layer is disposed on the at least one channel layer. Besides, multiple strip openings are configured to penetrate through the at least one barrier layer and at least one channel layer. The Schottky metal layer is disposed on the at least one barrier layer, across the strip openings and fills in the strip openings.

Abstract: A transistor including a buffer layer, a channel layer, a barrier layer, a superlattice structure, a gate, a source and a drain is provided. The buffer layer, the channel layer, the barrier layer, the superlattice structure and the gate are sequentially disposed on a substrate. The source and drain are disposed on the barrier layer and respectively at two sides of the superlattice structure, or on the channel layer and respectively at two sides of the barrier layer. The superlattice structure includes at least one first metal nitride layer and at least one second metal nitride layer stacked to each other. The average lattice constant of the superlattice structure is greater than that of GaN. The metal of each of the first and second metal nitride layers is at least one selected from the group consisting of Al, Ga and In. The first and second metal nitride layers are different.