Patents by Inventor JUNG-YI GUO
JUNG-YI GUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230269938Abstract: A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Inventors: Jung-Yi GUO, Chun-Min CHENG
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Publication number: 20200105782Abstract: A vertical channel structure including a substrate, a stack structure, and a channel structure is provided. The stack structure is disposed on the substrate. The channel structure is disposed in an opening that at least partially penetrates through the stack structure. The channel structure includes a first channel layer and a second channel layer. The first channel layer is disposed on a bottom of the opening. The second channel layer is disposed on the first channel layer. A resistance value of the first channel layer is less than a resistance value of the second channel layer.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 10340283Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.Type: GrantFiled: January 5, 2018Date of Patent: July 2, 2019Assignee: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 10312253Abstract: A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.Type: GrantFiled: March 14, 2017Date of Patent: June 4, 2019Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Chun-Min Cheng, Jung-Yi Guo
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Publication number: 20180269215Abstract: A method of forming a three-dimensional memory device is provided. Insulating layers and sacrificial layers are stacked alternatively on a substrate. At least one first opening is formed through the insulating layers and the sacrificial layers. Protection layers are formed on surfaces of the sacrificial layers exposed by the sidewall of the first opening. A charge storage layer is formed on the sidewall of the first opening and covers the protection layers. A channel layer is formed on the charge storage layer. The sacrificial layers and the protection layers are replaced with electrode layers. A three-dimensional memory device is further provided.Type: ApplicationFiled: March 14, 2017Publication date: September 20, 2018Applicant: MACRONIX International Co., Ltd.Inventors: Chun-Ling Chiang, Chun-Min Cheng, Jung-Yi Guo
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Publication number: 20180130822Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Applicant: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 9911754Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.Type: GrantFiled: October 7, 2016Date of Patent: March 6, 2018Assignee: MACRONIX International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20170125259Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.Type: ApplicationFiled: November 4, 2015Publication date: May 4, 2017Inventors: Jr-Meng WANG, Chih-Yuan WU, Kuanf-Wen LIU, Jung-Yi GUO, Chun-Min CHENG
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Patent number: 9627220Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.Type: GrantFiled: November 4, 2015Date of Patent: April 18, 2017Assignee: Macronix International Co., Ltd.Inventors: Jr-Meng Wang, Chih-Yuan Wu, Kuanf-Wen Liu, Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20160190153Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of fin structures, a plurality of conductor liner layers, a charge storage layer, a plurality of first conductor layers, and a plurality of filling pillars. The fin structures are disposed on the substrate, and a trench is formed between two adjacent fin structures. Each of the conductor liner layers covers a portion of sidewalls and a portion of top surfaces of the fin structures. The charge storage layer is disposed between the fin structures and the conductor liner layers. The first conductor layers cover the conductor liner layers and are electrically connected to the conductor liner layers. The filling pillars are disposed in the trenches and between the conductor liner layers and the first conductor layers.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 9287287Abstract: Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.Type: GrantFiled: December 18, 2013Date of Patent: March 15, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Patent number: 9224749Abstract: Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising forming an insulating base layer over a surface of a substrate. The method further comprises forming a multilayer over the insulating base layer, the multilayer having conducting and insulating layers. The method further comprises etching a pattern in the multilayer and forming a charge storage layer over the patterned multilayer. The method further comprises forming a protective silicon layer over the charge storage layer, followed by performing a heat treatment process.Type: GrantFiled: June 4, 2014Date of Patent: December 29, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20150357340Abstract: Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising forming an insulating base layer over a surface of a substrate. The method further comprises forming a multilayer over the insulating base layer, the multilayer having conducting and insulating layers. The method further comprises etching a pattern in the multilayer and forming a charge storage layer over the patterned multilayer. The method further comprises forming a protective silicon layer over the charge storage layer, followed by performing a heat treatment process.Type: ApplicationFiled: June 4, 2014Publication date: December 10, 2015Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20150171105Abstract: Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jung-Yi GUO, Chun-Min CHENG
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Patent number: 8872260Abstract: An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.Type: GrantFiled: June 5, 2012Date of Patent: October 28, 2014Assignee: Macronix International Co., Ltd.Inventors: Jung-Yi Guo, Chun-Min Cheng
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Publication number: 20130320484Abstract: An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: JUNG-YI GUO, CHUN-MIN CHENG