Patents by Inventor Jung-Yun Yun
Jung-Yun Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170219Abstract: A multilayer electronic component includes: a body having a dielectric layer and first and second internal electrodes alternately disposed with each other while having the dielectric layer interposed therebetween in a first direction; and an external electrode including a connection portion and a band portion extending from the connection portion onto first and second surfaces of the body, wherein the external electrode further includes an electrode layer connected to one of the first and second internal electrodes, a resin layer in contact with the first and second surfaces, and a conductive resin layer disposed on the electrode layer and extending to the resin layer, and L1??L1 when L1 indicates a second-directional size of the resin layer in the band portion, and L1? indicates a second-directional size of the conductive resin layer in the band portion.Type: ApplicationFiled: March 9, 2023Publication date: May 23, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Byung Woo KANG, Jung Min KIM, Hong Je CHOI, Ji Hye HAN, Hye Jin PARK, Su Yun YUN, Sang Wook LEE
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ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS
Publication number: 20230273880Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.Type: ApplicationFiled: May 4, 2023Publication date: August 31, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Chi Weon YOON, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun -
Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays
Patent number: 11681616Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.Type: GrantFiled: December 30, 2020Date of Patent: June 20, 2023Assignee: Samsung Electronics Co, Ltd.Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun -
Patent number: 11322205Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.Type: GrantFiled: March 18, 2020Date of Patent: May 3, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Won Park, Sang-Wan Nam, Ji Yeon Shin, Won Bo Shim, Jung-Yun Yun, Ji Ho Cho, Sang Gi Hong
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Patent number: 11227659Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: GrantFiled: September 15, 2020Date of Patent: January 18, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
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Patent number: 11200952Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.Type: GrantFiled: August 12, 2020Date of Patent: December 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Won Park, Sang-Wan Nam, Ji Yeon Shin, Won Bo Shim, Jung-Yun Yun, Ji Ho Cho, Sang Gi Hong
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Patent number: 11062775Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: GrantFiled: April 13, 2020Date of Patent: July 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
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ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS
Publication number: 20210117321Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN -
Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays
Patent number: 10909032Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.Type: GrantFiled: April 15, 2020Date of Patent: February 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun -
Publication number: 20210027840Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.Type: ApplicationFiled: March 18, 2020Publication date: January 28, 2021Inventors: Sang-Won PARK, Sang-Wan NAM, Ji Yeon SHIN, Won Bo SHIM, Jung-Yun YUN, Ji Ho CHO, Sang Gi HONG
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Publication number: 20210027841Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.Type: ApplicationFiled: August 12, 2020Publication date: January 28, 2021Inventors: Sang-Won PARK, Sang-Wan NAM, Ji Yeon SHIN, Won Bo SHIM, Jung-Yun YUN, Ji Ho CHO, Sang Gi HONG
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Publication number: 20200411103Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: ApplicationFiled: September 15, 2020Publication date: December 31, 2020Inventors: BONGSOON LIM, JUNG-YUN YUN, JI-SUK KIM, SANG-WON PARK
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ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS
Publication number: 20200242030Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.Type: ApplicationFiled: April 15, 2020Publication date: July 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN -
Publication number: 20200243140Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: BONGSOON LIM, JUNG-YUN YUN, JI-SUK KIM, SANG-WON PARK
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Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays
Patent number: 10671529Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.Type: GrantFiled: October 23, 2017Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun -
Patent number: 10658040Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: GrantFiled: November 15, 2016Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
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Patent number: 10366769Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.Type: GrantFiled: November 13, 2017Date of Patent: July 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-sung Cho, Il-han Park, Jung-yun Yun, Youn-ho Hong
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Patent number: 10346097Abstract: A storage device includes a nonvolatile memory device and a controller configured to send first data, an address, and a first command to the nonvolatile memory device. The controller also sends at least one data to the nonvolatile memory device after sending the first command. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the first command. When receiving the at least one data from the controller, the nonvolatile memory device is configured to continue to perform the program operation based on the first data and the at least one data.Type: GrantFiled: November 23, 2016Date of Patent: July 9, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Suk Kim, Jung-Yun Yun, Bongsoon Lim
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Publication number: 20180211715Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.Type: ApplicationFiled: November 13, 2017Publication date: July 26, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-sung CHO, Il-han PARK, Jung-yun YUN, Youn-ho HONG
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ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS
Publication number: 20180046574Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.Type: ApplicationFiled: October 23, 2017Publication date: February 15, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Chi Weon YOON, Dong Hyuk CHAE, Sang-Wan NAM, Jung-Yun YUN