Patents by Inventor Junggeun SHIN

Junggeun SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178000
    Abstract: A wafer dicing method includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, and separating the plurality of semiconductor devices from each other along the one or more internal cracks.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 30, 2024
    Inventors: Jesung Kim, Haemin Park, Heejae Nam, Junggeun Shin, Junho Yoon, Jungho Choi
  • Publication number: 20230420352
    Abstract: A semiconductor package, comprising: a first redistribution structure including a first redistribution via; a first package that is on an upper surface of the first redistribution structure and comprises a first pad; a second redistribution structure that is on a lower surface of the first redistribution structure and comprises a second redistribution via; a second semiconductor chip that is between the first redistribution structure and the second redistribution structure and comprises a connection pad; and a vertical connection structure that is between the first redistribution structure and the second redistribution structure, wherein the vertical connection structure is electrically connected to the first redistribution via and the second redistribution via, the connection pad is electrically connected to the second redistribution via, and the first redistribution via is electrically connected to the first pad.
    Type: Application
    Filed: January 13, 2023
    Publication date: December 28, 2023
    Inventors: Yeongbeom KO, Junyun KWEON, Wooju KIM, Heejae NAM, Haemin PARK, Junggeun SHIN
  • Patent number: 11854892
    Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Yoon, Jungchul Lee, Byungmoon Bae, Junggeun Shin, Hyunsu Sim
  • Publication number: 20230275037
    Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.
    Type: Application
    Filed: May 9, 2023
    Publication date: August 31, 2023
    Inventors: Hwayoung Lee, Heejae Nam, Byungmoon Bae, Junggeun Shin, Hyunsu Sim, Junho Yoon, Dongjin Lee
  • Patent number: 11676914
    Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwayoung Lee, Heejae Nam, Byungmoon Bae, Junggeun Shin, Hyunsu Sim, Junho Yoon, Dongjin Lee
  • Publication number: 20230082384
    Abstract: A substrate processing apparatus includes a chuck table including a mounting table having a mounting surface on which a substrate is mounted, wherein the mounting surface is a curved surface; and a laser supply head configured to irradiate the substrate attached to the mounting table with a laser beam.
    Type: Application
    Filed: April 27, 2022
    Publication date: March 16, 2023
    Inventors: Junho Yoon, Yeongbeom Ko, Hwayoung Lee, Junggeun Shin, Hyunsu Sim, Kwangyong Lee, Jongho Lee
  • Publication number: 20220208610
    Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Junho YOON, Jungchul LEE, Byungmoon BAE, Junggeun SHIN, Hyunsu SIM
  • Patent number: 11322405
    Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Yoon, Jungchul Lee, Byungmoon Bae, Junggeun Shin, Hyunsu Sim
  • Publication number: 20220059472
    Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.
    Type: Application
    Filed: March 29, 2021
    Publication date: February 24, 2022
    Inventors: Hwayoung Lee, Heejae Nam, Byungmoon Bae, Junggeun Shin, Hyunsu Sim, Junho Yoon, Dongjin Lee
  • Publication number: 20210159121
    Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.
    Type: Application
    Filed: June 23, 2020
    Publication date: May 27, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Junho YOON, Jungchul LEE, Byungmoon BAE, Junggeun SHIN, Hyunsu SIM