Abstract: Embodiments of the present invention provide a CXL device including a plurality of memories; a memory management unit configured to: configure at least one tier group in which the plurality of memories are classified and included; determine, based on metadata of a first memory of the plurality of memories, a grade of the first memory; and determine a tier group, to which the first memory belongs, of the at least one tier group according to the grade; and a memory processing unit configured to store data in at least one of the plurality of memories included in the at least one tier group, based on tiering information of the data.

Abstract: A CXL device includes at least one memory; a CXL controller configured to receive a request to access the at least one memory via a CXL interface, and to output a memory identifier indicating a first memory of the at least one memory, a command and a row address of the first memory based on the request; and a refresh controller configured to store the row address as a target row address of the first memory and further configured to generate a targeted refresh signal based on a number of receptions of the command for refreshing the target row address in the first memory.

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

Abstract: An electronic device includes a system on-chip that outputs a write clock and a write data signal, and a memory device that receives the write data signal based on the write clock and outputs a read data signal and a data strobe signal whose frequency is different from a frequency of the write clock. The memory device further includes a first interval oscillator, a second interval oscillator, and a temperature sensor. The electronic device performs a first training in initialization of the electronic device and performs a second training in an operation after the initialization. The memory device performs a counting operation during an operation of an interval oscillator in the second training and corrects a final count value with reference to temperature information of the memory device.

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to control an input/output operation of the memory cell array. When a memory defect detection command is received from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.

Abstract: A display apparatus includes a first substrate including a polymer resin, a protective layer on the first substrate, the protective layer including at least one selected from SiOCH, SiOC, SiOF, aromatic amine, diazonium tetrafluoroborate, and an aromatic diazonium compound, and a buffer layer on the protective layer, the buffer layer including a material different from a material included in the protective layer.

Abstract: A memory control device includes a threshold generating circuit, which is configured to set a first threshold for a first memory module electrically coupled to the memory control device. This first threshold is based on information associated with the first memory module. An attack defense circuit is also provided, which is configured to count an input row address, and decide a row address whose count value exceeds the first threshold among row addresses of the first memory module as an aggressor row address.

Abstract: A defense method of a memory device according to an embodiment includes obtaining a plurality of defense types to refresh a row of a memory cell array that is subjected to an attack, determining respective operation times for the defense types, and performing a refresh operation for the row of the memory cell array by switching among the defense types based on the respective operation times that were determined.

Abstract: A semiconductor device may include: a memory device that includes a memory cell, a page buffer, and a first switch having a first end that is electrically connected to a first node located at a bonding point of the memory cell and a second end that is connected to a second node located at the page buffer; and a memory controller that is configured to apply a pre-charge voltage to the first node and the second node in a first period, to close the first switch in a second period following the first period, and is configured to determine whether bonding between the memory cell and the first switch is defective based on a voltage of the second node after the first switch is closed.

Abstract: A test device includes a power supply circuit that is configured to supply an input voltage through a power voltage pin to a memory device under test, and a test controller, which is configured to: (i) transmit a command signal to the memory device, (ii) measure a first current flowing to the memory device through the power voltage pin at a first time point after transmitting the command signal, (iii) measure a second current flowing to the memory device through the power voltage pin at a second time point, which is different from the first time point, and (iv) compare the measured first current to the measured second current to thereby determine whether the memory device has a defect therein.

Abstract: A row decoder circuit includes a first transistor connected to a power supply node and a first node; a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a corresponding word line among the plurality of word lines; a plurality of second transistors connected between the first node and the plurality of second nodes; a plurality of third transistors connected between the plurality of second nodes and a power ground node; a comparator outputting a detection signal by receiving a voltage of the first node and a reference voltage. In a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the third transistors are turned off, so that the first node and the plurality of second nodes are charged.