Abstract: A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second column line connected to the other terminal of the memory cells adjacent to the one terminal of the memory cell storing the data to be readout, a second multiplexer selecting the sub-block including the second column line, a source selector selecting a third column line connected to the other terminal of the memory cell storing the data to be read out. The second multiplexer and precharge selector, when selecting, apply a first voltage to the second column line, and the source selector, when selecting, applies a second voltage to the third column line.

Abstract: A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second column line connected to the other terminal of the memory cells adjacent to the one terminal of the memory cell storing the data to be readout, a second multiplexer selecting the sub-block including the second column line, a source selector selecting a third column line connected to the other terminal of the memory cell storing the data to be read out. The second multiplexer and precharge selector, when selecting, apply a first voltage to the second column line, and the source selector, when selecting, applies a second voltage to the third column line.

Abstract: A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoder 110 is changed from the potential GND to the potential VDD, a pMOS transistor 125 is turned off, and the gate of nMOS transistor 124 comes to have a high impedance. Because of this, the self-boost effect acts on the gate of the nMOS transistor 124 to push up the source potential of the nMOS transistor 124. Consequently, the gate potential of the pMOS transistor 122 is abruptly raised, and this pMOS transistor 122 is turned off at high speed. The pMOS transistor 122 being turned off at high speed, the penetration current flowing through the transistors 121 and 122 is reduced and the electric potential of the word line WL falls at high speed.

Abstract: A non-volatile memory device includes: a first memory cell array having memory cells, in which one bit data is stored by a plurality of memory cells concurrently; and a second memory cell array having memory cells, in which one bit data is stored by a single memory cell. The device also includes a reference signal generating circuit that generates first and second reference signals, which are used for reading data stored in the first memory cell array and the second memory cell array, respectively; and a sense circuit that accesses the first and second memory cell arrays according to the first and second reference signals, respectively.

Abstract: A non-volatile memory device includes: a first memory cell array having memory cells, in which one bit data is stored by a plurality of memory cells concurrently; and a second memory cell array having memory cells, in which one bit data is stored by a single memory cell. The device also includes a reference signal generating circuit that generates first and second reference signals, which are used for reading data stored in the first memory cell array and the second memory cell array, respectively; and a sense circuit that accesses the first and second memory cell arrays according to the first and second reference signals, respectively.

Abstract: A word-line driving circuit drives the word lines of a non-volatile semiconductor memory to different potentials to read, write, and erase data in memory cells coupled to the word lines. A ground potential is supplied to non-driven word lines through respective switching elements. The data in the memory cells coupled to some or all of the word lines can be erased simultaneously by driving those word lines to an erasing potential. When this is done, a mitigating potential intermediate between the ground potential and the erasing potential is supplied to the switching elements of the driven word lines, thereby reducing current leakage through these switching elements, which are switched off.

Abstract: A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoder 110 is changed from the potential GND to the potential VDD, a pMOS transistor 125 is turned off, and the gate of nMOS transistor 124 comes to have a high impedance. Because of this, the self-boost effect acts on the gate of the nMOS transistor 124 to push up the source potential of the nMOS transistor 124. Consequently, the gate potential of the pMOS transistor 122 is abruptly raised, and this pMOS transistor 122 is turned off at high speed. The pMOS transistor 122 being turned off at high speed, the penetration current flowing through the transistors 121 and 122 is reduced and the electric potential of the word line WL falls at high speed.

Abstract: A word-line driving circuit drives the word lines of a non-volatile semiconductor memory to different potentials to read, write, and erase data in memory cells coupled to the word lines. A ground potential is supplied to non-driven word lines through respective switching elements. The data in the memory cells coupled to some or all of the word lines can be erased simultaneously by driving those word lines to an erasing potential. When this is done, a mitigating potential intermediate between the ground potential and the erasing potential is supplied to the switching elements of the driven word lines, thereby reducing current leakage through these switching elements, which are switched off.

Abstract: A nonvolatile semiconductor memory device comprising a plurality of memory cells each having a transistor including a floating gate electrode as a constituent are arranged on a silicon substrate in a matrix, wherein bit lines have hierarchical structures and comprise at least a main bit line 1 and a sub-bit line 2, and a plurality of sub-bit line selection transistors 4 provided between the main bit line 1 and sub-bit line 2 which transistor 4 are respectively selectively activated depending on given row address lines, wherein a voltage applied to each gate electrode of the sub-bit line selection transistor 4 which is selected and activated when data is erased from or written on each memory cell is rendered the same as that applied to each gate electrode of the sub-bit line selection transistor 4 which becomes non-activated when not selected.

Abstract: It is an object of the invention to provide a flash memory with a fast reading speed and good read disturb resistance. This flash memory comprises a memory cell block having FAMOS transistors arranged in a matrix form; a plurality of word lines connected to the control gates of transistors in the same row; a plurality of bit lines connected to the drains of transistors in the same column; a source line connected in common to the sources of all transistors; and a driver circuit for charging the source line. The driver circuit charges the source line and not the bit line when reading data. In addition, the driver circuit performs accelerated charging at the start of charging the source line and thereafter performs normal charging.

Abstract: A reset pulse signal generating circuit includes an output node with an output circuit connected thereto that outputs the reset pulse signal, and a first MOS transistor having a first conductivity type connected between a first power supply and the output node. The first MOS transistor is turned on responsive to a write signal. The circuit further includes a second MOS transistor having a second conductivity type connected between the output node and a second power supply, and a power supply transition detector connected to the first and second power supplies and the second MOS transistor. The power supply transition detector outputs a transfer signal having a level determined by a level of the power supplies when the write signal is in an inactive state. The power supply transition detector outputs the transfer signal having a predetermined level when the write signal is in the active state.

Abstract: It is an object of the invention to provide a flash memory with a fast reading speed and good read disturb resistance. This flash memory comprises a memory cell block having FAMOS transistors arranged in a matrix form; a plurality of word lines connected to the control gates of transistors in the same row; a plurality of bit lines connected to the drains of transistors in the same column; a source line connected in common to the sources of all transistors; and a driver circuit for charging the source line. The driver circuit charges the source line and not the bit line when reading data. In addition, the driver circuit performs accelerated charging at the start of charging the source line and thereafter performs normal charging.

Abstract: A nonvolatile semiconductor memory device comprising a plurality of memory cells each having a transistor including a floating gate electrode as a constituent are arranged on a silicon substrate in a matrix, wherein bit lines have hierarchical structures and comprise at least a main bit line 1 and a sub-bit line 2, and a plurality of sub-bit line selection transistors 4 provided between the main bit line 1 and sub-bit line 2 which transistor 4 are respectively selectively activated depending on given row address lines, wherein a voltage applied to each gate electrode of the sub-bit line selection transistor 4 which is selected and activated when data is erased from or written on each memory cell is rendered the same as that applied to each gate electrode of the sub-bit line selection transistor 4 which becomes non-activated when not selected.

Abstract: A nonvolatile semiconductor memory device comprising a plurality of memory cells each having a transistor including a floating gate electrode as a constituent are arranged on a silicon substrate in a matrix, wherein bit lines have hierarchical structures and comprise at least a main bit line 1 and a sub-bit line 2, and a plurality of sub-bit line selection transistors 4 provided between the main bit line 1 and sub-bit line 2 which transistor 4 are respectively selectively activated depending on given row address lines, wherein a voltage applied to each gate electrode of the sub-bit line selection transistor 4 which is selected and activated when data is erased from or written on each memory cell is rendered the same as that applied to each gate electrode of the sub-bit line selection transistor 4 which becomes non-activated when not selected.

Abstract: A non-volatile semiconductor memory device has a data latch that stores data to be written into memory cells, and functions as a sense amplifier for data read from the memory cells. Read data and write data have opposite polarities in the data latch. A data polarity control circuit in the memory device generates a selection signal indicating whether the data latch stores read data or write data. A data polarity switch generates externally readable data by outputting read data stored in the data latch, and by inverting write data stored in the data latch.

Abstract: After specific data are stored at individual page latches 80.sub.1 to 80.sub.m, the latch data stored at the page laches 80.sub.1 to 80.sub.m are written into one-word memory cells 10.sub.1j to 10.sub.mj.When the data writing is completed, the individual sets of latch data stored at the page latches 80.sub.1 to 80.sub.m are output to bit lines BL.sub.1 to BL.sub.m, to be compared against the memory data stored in the individual memory cells 10.sub.1j to 10.sub.mj.These comparison results are re-stored at the individual page latches 80.sub.1 to 80.sub.m. At this point, if the memory data stored in the memory cells 10.sub.1j to 10.sub.mj have been written correctly, L level data are written at the corresponding page latches 80.sub.i, whereas if they have not been written correctly, H level data are written at the page latches 80.sub.i.The data that have been re-stored at the individual page latches 80.sub.i are output to a data verification line DL to which a verification unit 100 is connected.