Abstract: A semiconductor storage device includes a plurality of memory cells, a selecting circuit for selecting, in accordance with address information supplied from an external unit, a memory cell from among the plurality of memory cells, there being a case where a memory cell identified by the address information supplied from the external unit is not present in the plurality of memory cells, a data line to which the plurality of memory cells are coupled, data read out from the selected memory cell being transmitted through the data line, the data line being able to be in a floating state when a memory cell identified by address information is not present in the plurality of memory cells, an amplifier for amplifying the data transmitted through the data line, a latching circuit for latching a potential level of data which has been supplied to the data line, and a control circuit for controlling the latching circuit so that the latching circuit is inactive in a predetermined period including a time at which the data

Abstract: A master-slice type semiconductor integrated circuit device includes a first transistor, and a second transistor. The first and second transistors are arranged side by side in a first direction. The first and second transistors respectively have first and second gate electrodes extending in a second direction perpendicular to the first direction. The first gate electrode has a first portion in which two gate contacts arranged in the first direction can be made. The second gate electrode has a second portion in which two gate contacts arranged in the first direction can be made.

Abstract: A semiconductor integrated circuit device includes a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns. The logic cells respectively have input terminals and output terminals. Also, the device includes interconnection lines mutually connecting the logic cells via the input and output terminals of the logic cells so that desired logic circuits are formed, and a plurality of switches which are respectively provided for the logic cells and selectively connect the output terminals of the logic cells to the interconnection lines. Further, the device includes a test circuit for directly supplying the input terminals of the logic cells with desired data used for testing the semiconductor integrated circuit device in a state where a plurality of switches selectively disconnect the output terminals of the logic cells from the interconnection lines. The output line of a cell is disconnected from the interconnection line to the input of the following cell.

Abstract: A semiconductor memory device has a memory part, first and second write bit lines coupled to the memory part and used exclusively for writing information into the memory part and first and second read bit lines coupled to the memory part and used exclusively for reading information, held in the memory part, from the memory part. A short-circuiting circuit short-circuits the first and second read bit lines and thereby sets them to the same potential, in a write mode of operation of the semiconductor memory device in which information is written into the memory part via the first and second write bit lines. The short-circuiting circuit permits a read operation to be performed immediately following a write operation, at a high speed.

Abstract: A circuit arrangement formed on an IC chip includes a first type block and a second type block. The first type block has a plurality of cells arranged into rows and columns and a plurality of transistors respectively provided for the cells. Each of the transistors has a first terminal coupled to a corresponding one of the cells, a second terminal and a gate terminal. The second type block is a block which is not required to be test in a way identical to that for the first type block. A probe line driver tests the cells in the first type block, and is located along a first edge of the first type block. A plurality of probe lines extend from the probe line driver and run in the first type block. Each of the probe lines is connected to the gate of a corresponding one of the transistors. A sense circuit senses data read out from the cells via a plurality of sense lines running in the first type block. Each of the sense lines is connected to the second terminal of a corresponding one of the transistors.

Abstract: A semiconductor memory device in which dual ports are provided for selecting a specific memory cell from a memory cell matrix includes a driving state detection unit for detecting the state of driving word lines of the two ports and delivering a detection signal based on the detection, where one of the ports is in the writing state with regard to the memory cell, and a bit line short-circuiting unit responsive to the detection signal from the driving state detection unit for realizing a short-circuit between predetermined bit lines.

Abstract: A partial random access memory includes a plurality of memory cells arrayed in matrix form, a plurality of pairs of bit lines extending in a column direction, each of the plurality of memory cells being coupled to corresponding one of pairs of bit lines, and a plurality of word lines including a plurality of first and second word lines. One first word line and one second word line are paired and arranged on both sides of an arrangement of the memory cells in a row direction. Each of the plurality of memory cells is connected to at least one of the first and second word lines. An activating circuit coupled to the plurality of word lines separately activates the first and second word lines, depending on an address signal supplied from an external circuit, thereby independently selecting the first and second word lines. An input/output circuit coupled to the plurality of bit lines writes input data into corresponding memory cells and reads out output data from corresponding memory cells.

Abstract: A semiconductor integrated circuit device comprising a first circuit forming a random logic and outputting a plurality of first parallel data of plural bits, a second circuit which receives the plurality of first parallel data and supplies a plurality of second parallel data of plural bits to the first circuit, and a test circuit which divides a part of external parallel data of plural bits smaller in number than the first parallel data into a plurality of third parallel data of plural bits in such a manner that the plurality of third parallel data correspond in number to the plurality of first parallel data.