Abstract: There is provided an electrode structure for a polymer electrolyte fuel cell having excellent power generation performance and excellent durability and a method for manufacturing the same. Also provided is a polymer electrolyte fuel cell including the electrode structure and an electrical apparatus and a transport apparatus using the polymer electrolyte fuel cell. The electrode structure includes a polymer electrolyte membrane 2 sandwiched between a pair of electrode catalyst layers 1, 1 containing carbon particles supporting catalyst particles. The polymer electrolyte membrane 2 is made of a sulfonated polyarylene-based polymer. The sulfonated polyarylene-based polymer has an ion exchange capacity in the range of 1.7 to 2.3 meq/g, and the polymer contains a component insoluble in N-methylpyrrolidone in an amount of 70% or less relative to the total amount of the polymer, after the polymer is subjected to heat treatment for exposing it under a constant temperature atmosphere of 12° C. for 200 hours.

Abstract: VSS 302 is provided to a gate portion 304 and VDD 301 is provided to a source portion 305 and a drain portion 306 of a MOS transistor which constitutes a decoupling capacitor, and a potential NWVDD 303 different from that provided to the source portion 305 and the drain portion 306 is provided to a substrate portion 307. If NWVDD 303 is set higher than VDD 301, a depletion layer 309 is spread, so that a leakage current can be reduced instead of reducing a capacitance of the decoupling capacitor. In addition, if NWVDD 303 is set lower than VDD 301 so as not to cause latchup, the depletion layer 309 is reduced, so that the capacitance of the decoupling capacitor can be increased. By changing the potential NWVDD 303 provided to the substrate portion 307, a capacitance value and a leakage current value of the decoupling capacitor can be controlled.

Abstract: In a standard cell in which a substrate voltage control technique is implemented, a plurality of normal power supply wires are disposed at previously set positions. Therefore, when the standard cell is disposed adjacent to another standard cell having such normal power supply wires, these normal power supply wires are connected to each other. In addition, the standard cell is provided with a substrate power supply terminal which is not connected to that of the other standard cell when the other standard cell is disposed adjacent to the standard cell. Therefore, when a semiconductor integrated circuit is composed of a plurality of the standard cells, a wiring route of an inter-cell substrate power supply wire, or the like can be freely set.

Abstract: By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the adjacent wiring 4, it is made possible to change the delay of the signal S3 in the signal wiring 3 in several picoseconds, by using crosstalk with the signal S4 in the signal wiring 4.The inventive delay control circuit device can be provided by simply adding adjacent wiring 4 and a control circuit 13 to signal wiring 3. This implements a delay control circuit device for semiconductor integrated circuits that is capable of controlling a signal delay in several picoseconds without increasing the circuit scale.

Abstract: In order to provide a membrane electrode assembly and a fuel cell in which the thickness of the solid polymer electrolyte membrane is thin by enhancing self-protection of the solid polymer electrolyte membrane, a membrane electrode assembly comprises a solid polymer electrolyte membrane and a pair of gas diffusion electrode layer having catalyst layers and gas diffusion layers. The catalyst layers of the gas diffusion electrode layer sandwich the solid polymer electrolyte membrane, one surface of the solid polymer electrolyte membrane is covered by the gas diffusion electrode layer and the other surface of the solid polymer electrolyte membrane extends over the gas diffusion electrode layer, and ends of the catalyst layer of one gas diffusion electrode layer are disposed to be offset to ends of the catalyst layer of the other gas diffusion electrode layer.

Abstract: The present invention provides a complex, which comprises a cationic liposome comprising 2-O-(2-diethylaminoethyl)carbamoyl-1,3-O-dioleoylglycerol and a phospholipid as main ingredients, and an oligo nucleic acid which is carried on the liposome. Also, the present invention provides a pharmaceutical composition containing the complex to be used for treating or preventing diseases caused by a target molecule of the oligo nucleic acid (target DNA, target RNA, target protein) since it is possible to administer the complex in vivo and to put the complex into practical use as a medicament because the complex can exhibit pharmacological efficacy in vivo.

Abstract: A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.

Abstract: In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node approximately drops to High*{C1/(C1+C2)} from High, where C1 represents the capacitance of the precharge node and C2 represents the capacitance of the intermediate node. Thereafter, with the charge from a power supply, the precharge node returns to High. At this charge sharing time, the amount of charge supply from the power supply is adjusted to suppress voltage drop of the precharge node, thereby reducing noise.

Abstract: A semiconductor integrated circuit comprises: a first standard cell which includes a first logic circuit and a first switch for controlling current supply to the first logic circuit; and a second standard cell which includes a second logic circuit and a second switch for controlling current supply to the second logic circuit. The first switch is shared with the second standard cell as the second switch.

Abstract: In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node approximately drops to High*{C1/(C1+C2)} from High, where C1 represents the capacitance of the precharge node and C2 represents the capacitance of the intermediate node. Thereafter, with the charge from a power supply, the precharge node returns to High. At this charge sharing time, the amount of charge supply from the power supply is adjusted to suppress voltage drop of the precharge node, thereby reducing noise.

Abstract: In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in final gate dimension, suppressing variation in characteristics of the standard cell.

Abstract: In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node approximately drops to High*{C1/(C1+C2)} from High, where C1represents the capacitance of the precharge node and C2 represents the capacitance of the intermediate node. Thereafter, with the charge from a power supply, the precharge node returns to High. At this charge sharing time, the amount of charge supply from the power supply is adjusted to suppress voltage drop of the precharge node, thereby reducing noise.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: A membrane electrode assembly includes an anode, a cathode, and a solid polymer electrolyte membrane interposed between the anode and the cathode. The anode and the cathode include gas diffusion layers and electrode catalyst layers. Mixture layers are provided over predetermined areas H around surfaces of the electrode catalyst layers. The electrode catalyst layers and adhesive layers are mixed in the mixture layers, respectively.

Abstract: VSS 302 is provided to a gate portion 304 and VDD 301 is provided to a source portion 305 and a drain portion 306 of a MOS transistor which constitutes a decoupling capacitor, and a potential NWVDD 303 different from that provided to the source portion 305 and the drain portion 306 is provided to a substrate portion 307. If NWVDD 303 is set higher than VDD 301, a depletion layer 309 is spread, so that a leakage current can be reduced instead of reducing a capacitance of the decoupling capacitor. In addition, if NWVDD 303 is set lower than VDD 301 so as not to cause latchup, the depletion layer 309 is reduced, so that the capacitance of the decoupling capacitor can be increased. By changing the potential NWVDD 303 provided to the substrate portion 307, a capacitance value and a leakage current value of the decoupling capacitor can be controlled.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: Leaf springs have improved durability in spite of using inexpensive spring steel such as SUP9 and SUP11 as materials. While a spring main body, made of the spring steel in which Brinell hardness is under 555 HBW and not less than 388 HBW (corresponding to a diameter of under 2.70 mm of hardness and not less than 3.10 mm of hardness on a Brinell ball mark), is maintained at 150 to 400° C., the load is applied in the direction in which the spring main body is to be used, and the first shotpeening is performed at the plane where the tensile stress acts.

Abstract: A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.

Abstract: The invention provides a manufacturing process for MEA that enables sufficient bond strength among an electrolyte membrane and electrode substrates even when the electrolyte membrane comprises a heat-resistant material such as an aromatic polymer.

Abstract: The semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a resistor device connected between the first node and the second node; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the first node and controlling whether or not the output node is set at the second logic level.