Patents by Inventor Junichiro Kobayashi

Junichiro Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161298
    Abstract: The present invention improves estimation accuracy. An information processing system includes: an acquisition unit (102) configured to acquire adjustment information based on a feature value of learning data used for generation of a learned model that estimates a health condition of a patient or a subject; a processing unit (103) configured to perform processing on a biological sample to be judged on the basis of the adjustment information; and an estimation unit (104) configured to estimate a diagnosis result by inputting measurement data acquired by the processing to the learned model.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 16, 2024
    Inventors: SHIORI SASADA, KAZUKI AISAKA, KENJI YAMANE, JUNICHIRO ENOKI, YOSHIYUKI KOBAYASHI, MASATO ISHII, KENJI SUZUKI
  • Publication number: 20240120140
    Abstract: A plurality of through-hole conductors include a first through-hole conductor and a second through-hole conductor between coil conductors adjacent each other. Each of the first through-hole conductor and the second through-hole conductor includes a first end and a second end. The first end included in the second through-hole conductor is coupled to the second end included in the first through-hole conductor, and has a width larger than a width of the second end included in the first through-hole conductor. The first end included in the first through-hole conductor has a width larger than the width of the second end included in the first through-hole conductor. The second end included in the second through-hole conductor has a width smaller than the width of the first end included in the second through-hole conductor.
    Type: Application
    Filed: June 15, 2023
    Publication date: April 11, 2024
    Applicant: TDK CORPORATION
    Inventors: Noriaki HAMACHI, Toshinori MATSUURA, Junichiro URABE, Kota OIKAWA, Yuto SHIGA, Youichi KAZUTA, Yuichi TAKUBO, Shunya SUZUKI, Xuran GUO, So KOBAYASHI
  • Patent number: 7297993
    Abstract: A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion having a base layer formed on an upper face thereof, and a base electrode contacts with the base layer and has a floating extension which extends from the semiconductor mesa portion to a space on the outer side with respect to the semiconductor mesa portion. The floating extension is used as a contact portion for a base wiring line to the base electrode.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: November 20, 2007
    Assignee: Sony Corporation
    Inventor: Junichiro Kobayashi
  • Publication number: 20070243689
    Abstract: A semiconductor device, able to be produced while suppressing the occurrence of mesa shaped abnormalities without restriction as to the pattern layout, the type of etchant used, etc., provided with a semiconductor mesa portion including a stack of a collector layer, a base layer, and an emitter layer on a substrate and functioning as an active region of a bipolar transistor, a base contact pad mesa portion separated from this by a predetermined distance and having a height the same as the top surface of the base layer, and a conductor layer integrally formed with a base electrode connected to the base layer, a base contact pad electrode formed on the base contact pad mesa portion in a region other than near the edges of the top surface of the base contact pad mesa portion, and an interconnect connecting these, and a method of producing the same.
    Type: Application
    Filed: March 20, 2007
    Publication date: October 18, 2007
    Applicant: Sony Corporation
    Inventor: Junichiro Kobayashi
  • Patent number: 7015518
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: March 21, 2006
    Assignee: Sony Corporation
    Inventor: Junichiro Kobayashi
  • Patent number: 7011997
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: March 14, 2006
    Assignee: Sony Corporation
    Inventor: Junichiro Kobayashi
  • Patent number: 7012287
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: March 14, 2006
    Assignee: Sony Corporation
    Inventor: Junichiro Kobayashi
  • Publication number: 20060017065
    Abstract: A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion having a base layer formed on an upper face thereof, and a base electrode contacts with the base layer and has a floating extension which extends from the semiconductor mesa portion to a space on the outer side with respect to the semiconductor mesa portion. The floating extension is used as a contact portion for a base wiring line to the base electrode.
    Type: Application
    Filed: July 12, 2005
    Publication date: January 26, 2006
    Inventor: Junichiro Kobayashi
  • Publication number: 20050161705
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Application
    Filed: March 21, 2005
    Publication date: July 28, 2005
    Inventor: Junichiro Kobayashi
  • Publication number: 20050161736
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Application
    Filed: March 21, 2005
    Publication date: July 28, 2005
    Inventor: Junichiro Kobayashi
  • Publication number: 20050116252
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Application
    Filed: November 17, 2004
    Publication date: June 2, 2005
    Inventor: Junichiro Kobayashi
  • Patent number: 6853016
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: February 8, 2005
    Assignee: Sony Corporation
    Inventor: Junichiro Kobayashi
  • Publication number: 20040211978
    Abstract: A semiconductor device, able to be produced while suppressing the occurrence of mesa shaped abnormalities without restriction as to the pattern layout, the type of etchant used, etc., provided with a semiconductor mesa portion including a stack of a collector layer, a base layer, and an emitter layer on a substrate and functioning as an active region of a bipolar transistor, a base contact pad mesa portion separated from this by a predetermined distance and having a height the same as the top surface of the base layer, and a conductor layer integrally formed with a base electrode connected to the base layer, a base contact pad electrode formed on the base contact pad mesa portion in a region other than near the edges of the top surface of the base contact pad mesa portion, and an interconnect connecting these, and a method of producing the same.
    Type: Application
    Filed: March 22, 2004
    Publication date: October 28, 2004
    Inventor: Junichiro Kobayashi
  • Publication number: 20030151063
    Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in step coverage property at a gate electrode provided on an operating region, and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include operating region composed of multilayer films such as a channel layer, an electron supplying layer and other semiconductor layer and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.
    Type: Application
    Filed: January 10, 2003
    Publication date: August 14, 2003
    Inventor: Junichiro Kobayashi
  • Patent number: 5006478
    Abstract: A method for manufacturing a semiconductor device, comprising the steps of forming a first resist layer, an intermediate layer and a second resist layer sequentially on a substrate; forming an aperture by removing a portion of the second resist layer where a T-shaped gate is to be later formed; over-etching a portion of the intermediate layer opposed to the aperture thereby forming in the intermediate layer an aperture larger than the first-mentioned aperture; and forming, in the first resist layer, an aperture which is smaller than the aperture in the second resist layer which is positioned inside thereof. Due to the combination of such successive steps, the lift-off process required to form a desires T-shaped gate can be substantially improved.
    Type: Grant
    Filed: July 24, 1990
    Date of Patent: April 9, 1991
    Assignee: Sony Corporation
    Inventors: Junichiro Kobayashi, Shigeru Hiramatsu, Hidemi Takakuwa