Patents by Inventor Junji Aoike

Junji Aoike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit having anti-fuse, method of fabricating, and method of writing data in the same
    Patent number: 6710415
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: March 23, 2004
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike
  • Semiconductor integrated circuit having anti-fuse, method of fabricating, and method of writing data in the same
    Publication number: 20030214014
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Application
    Filed: June 16, 2003
    Publication date: November 20, 2003
    Applicant: KAWASAKI MICROELECTRONICS, INC.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike
  • Semiconductor integrated circuit having anti-fuse, method of fabricating, and method of writing data in the same
    Patent number: 6608355
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: August 19, 2003
    Assignee: Kawasaki Microelectronics, Ltd.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike
  • Semiconductor integrated circuit having anti-fuse, method of fabricating, and method of writing data in the same
    Publication number: 20020117724
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 29, 2002
    Applicant: KAWASAKI MICROELECTRONICS INC.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike