Abstract: According to one embodiment, a low-pass filter operation circuit constitutes a serial interface, which enables communication conforming to the serial bus standard including IEEE 1394 & USB 3.0, together with a timer register, a packet receiving circuit, and a packet transmitting circuit. The low-pass filter operation circuit performs a correction of gradually increasing or decreasing an internal timer value counted by the timer register by a unit count value thereof, thereby converging the deviation. A timer operation circuit calculates a timer reference value, corresponding to the timing at which sync. should be done next, common to cameras, based on a timer value in the timer register, and a frame rate generated by CPU.

Abstract: According to one embodiment, a low-pass filter operation circuit constitutes a serial interface, which enables communication conforming to the serial bus standard including IEEE 1394 & USB 3.0, together with a timer register, a packet receiving circuit, and a packet transmitting circuit. The low-pass filter operation circuit performs a correction of gradually increasing or decreasing an internal timer value counted by the timer register by a unit count value thereof, thereby converging the deviation. A timer operation circuit calculates a timer reference value, corresponding to the timing at which sync. should be done next, common to cameras, based on a timer value in the timer register, and a frame rate generated by CPU.

Abstract: An adder provided in a trigger delay control circuit adds the clock fixed delay value issued by the CPU to the clock timestamp information obtained by a software trigger detection circuit to output a timestamp information including a trigger delay of a fixed time, and a comparator compares the cycle timer value output from the cycle timer operation circuit with the timestamp output from the adder and including the trigger delay of the fixed time to output a trigger signal to the synchronization signal generation circuit for instructing to start exposure when the cycle timer value exceeds the timestamp including the trigger delay of the fixed time.

Abstract: An adder provided in a trigger delay control circuit adds the clock fixed delay value issued by the CPU to the clock timestamp information obtained by a software trigger detection circuit to output a timestamp information including a trigger delay of a fixed time, and a comparator compares the cycle timer value output from the cycle timer operation circuit with the timestamp output from the adder and including the trigger delay of the fixed time to output a trigger signal to the synchronization signal generation circuit for instructing to start exposure when the cycle timer value exceeds the timestamp including the trigger delay of the fixed time.

Abstract: In a camera system wherein video signals generated by a plurality of cameras are transmitted in units of image frames to a host PC, in a shared isochronous band through an IEEE1394 bus, each of the cameras comprises an asynchronous streaming-packet receiving circuit configured to receive an asynchronous streaming packet transmitted to the IEEE1394 bus, an asynchronous streaming-packet transmitting circuit configured to transmit an asynchronous streaming packet to the IEEE1394 bus, and an image output switch configured to supply a video signal generated by any camera, in the form of an isochronous packet, to the IEEE1394 bus under the control of the asynchronous streaming-packet receiving circuit.

Abstract: An imaging unit has a plurality of pixels arrayed two-dimensionally therein, and each pixel has an independent address, and is formed such that each pixel may be assigned with a reading address. A signal processing unit can generate an address for specifying arbitrary plural regions in the imaging region when an imaging signal is read out from the imaging unit.

Abstract: An imaging unit has a plurality of pixels arrayed two-dimensionally therein, and each pixel has an independent address, and is formed such that each pixel may be assigned with a reading address. A signal processing unit can generate an address for specifying arbitrary plural regions in the imaging region when an imaging signal is read out from the imaging unit.