Abstract: A semiconductor integrated circuit includes a substrate having a main surface to which a first stress is applied; a first channel conductive field effect transistor placed in a first region of the main surface of the substrate, the carrier mobility of a channel of the first channel conductive field effect transistor being improved by the first stress; and a second channel conductive field effect transistor placed in a second region of the main surface of the substrate, and receiving a second stress at a channel thereof, the second stress being opposite to the first stress, the carrier mobility of the channel of the second channel conductive field effect transistor being improved by the second stress, and the second region being independent from the first region.

Abstract: A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate having isolation regions, and a MIS transistor comprising a gate electrode formed above the semiconductor substrate with a gate insulating film interposed therebetween, and a pair of contact layers formed on the semiconductor substrate sandwiching the gate electrode, the contact layers having an interfacial layer at an interface between the semiconductor substrate and the contact layers, the interfacial layer comprising a metal silicide containing at least one selected from a group consisting of Er, Gd, Tb, Dy, Ho, Tm, Yb, Lu, and Pt.

Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

Abstract: A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1?a Gea (0?a?1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1?c Gec (0?c?1, a?c).

Abstract: A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.

Abstract: A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

Abstract: A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein.

Abstract: A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load.

Abstract: A nonvolatile semiconductor storage element which has a charge stored layer as a floating gate, and whose storage time is made sufficiently long. The storage element comprises a channel region formed between a source region and a drain region; first and second tunnel insulator layers formed over the channel region and through which electrons can directly tunnel quantum-mechanically; and a conductive particle layer which is sandwiched in between the first and second tunnel insulator layers; the charge stored layer being formed on the second tunnel insulator layer. An energy level at which the information electron in the charge stored layer is injected is lower than the energy level of a conduction band edge in the channel region.

Abstract: A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

Abstract: A nonvolatile semiconductor storage element which has a charge stored layer as a floating gate, and whose storage time is made sufficiently long. The storage element comprises a channel region formed between a source region and a drain region; first and second tunnel insulator layers formed over the channel region and through which electrons can directly tunnel quantum-mechanically; and a conductive particle layer which is sandwiched in between the first and second tunnel insulator layers; the charge stored layer being formed on the second tunnel insulator layer. An energy level at which the information electron in the charge stored layer is injected is lower than the energy level of a conduction band edge in the channel region.

Abstract: A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

Abstract: A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load.

Abstract: A semiconductor integrated circuit (IC) device has a silicon-on-insulator substrate having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a silicon layer formed on the insulating film. The semiconductor IC device includes at least one semiconductor device formed on the semiconductor substrate, and at least one semiconductor device formed on the silicon layer and operated with a power-supply voltage different from a power-supply voltage for the semiconductor device formed on the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate having an element region on the main surface thereof, an element isolation region formed to surround the element region on the main surface of the semiconductor substrate, a gate electrode formed over the element region with a gate insulating film disposed therebetween, a first and a second impurity diffusion region formed on a surface of the element region on both sides of at least part of the gate electrode, a first channel region formed in the surface of the element region below the gate electrode between the first and the second impurity diffusion region when a first preset voltage is applied to the gate electrode, and a first tunnel diode formed in a first interface region between the first impurity diffusion region and the first channel region when the first preset voltage is applied to the gate electrode, wherein the first interface region in which the first tunnel diode is formed is formed in position separated from the element isolation region

Abstract: Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor formed in the SOI substrate and an Esaki diode is positioned on the MOS transistor. The memory device also comprises a memory cell provided with a plurality of tunnel diodes connected to one of the impurity regions constituting the FET formed in the semiconductor substrate, and another memory cell provided with an Esaki diode formed in an self-alignment by a solid phase diffusion. In manufacturing the semiconductor memory device, the MOS transistor and the Esaki diode, which collectively form a memory cell, are integratedly formed one upon the other. The MOS transistor is formed in a semiconductor substrate using an SOI structure so as to prepare a memory cell which does not include a parasitic pn-junction.