Patents by Inventor Junji Sugamoto

Junji Sugamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110245956
    Abstract: A management system includes a variable-period setting unit that sets a variable period in which quality-control values vary. Then, a retrieving unit retrieves events sandwiching the variable period. The events can be a maintenance of the semiconductor manufacturing device and/or a change of a correction value. An analysis-period setting unit sets an analysis period for analyzing a cause of variation of the quality-control values between the events retrieved by the retrieving unit.
    Type: Application
    Filed: June 8, 2011
    Publication date: October 6, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Junji Sugamoto, Masafumi Asano
  • Patent number: 7979154
    Abstract: A management system includes a variable-period setting unit that sets a variable period in which quality-control values vary. Then, a retrieving unit retrieves events sandwiching the variable period. The events can be a maintenance of the semiconductor manufacturing device and/or a change of a correction value. An analysis-period setting unit sets an analysis period for analyzing a cause of variation of the quality-control values between the events retrieved by the retrieving unit.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Junji Sugamoto, Masafumi Asano
  • Patent number: 7970486
    Abstract: A method for controlling a semiconductor manufacturing apparatus for processing wafers divided for each lot, has acquiring quality control value data group containing quality control value data of wafers in a plurality of lots previously processed, and an equipment engineering system parameter group containing equipment engineering system parameters corresponding to the wafers; creating a prediction formula of quality control value data, acquiring a first equipment engineering system parameters; inputting the first equipment engineering system parameters to the prediction formula, and performing calculation to predict first quality control value data of the wafers in the first lot; determining processing of the wafers corresponding to the first quality control value data; acquiring measured first quality control value data of the wafers in the first lot; replacing the quality control value data corresponding to the wafers in the first processed lot; updating the prediction formula.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Junji Sugamoto, Masafumi Asano
  • Patent number: 7831330
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: November 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Patent number: 7742834
    Abstract: According to the present, there is proved a semiconductor fabrication apparatus management system having: a sensor which monitors and outputs a plurality of apparatus parameters of a semiconductor fabrication apparatus which fabricates a semiconductor device; a measurement unit which measures a dimensional value of the semiconductor device, and outputs the dimensional value as dimensional data; an apparatus parameter storage unit which stores the apparatus parameters; a dimensional data storage unit which stores the dimensional data; an apparatus parameter controller which calculates predicted dimensional data by extracting the dimensional data from the dimensional data storage unit, and controls at least one of the plurality of apparatus parameters on the basis of the predicted dimensional data; and an abnormality factor extraction unit which analyzes correlations between the controlled apparatus parameter and other apparatus parameters, and extracts an abnormal apparatus parameter on the basis of a calculat
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: June 22, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Junji Sugamoto, Masafumi Asano
  • Patent number: 7700381
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 20, 2010
    Assignee: Kabushikia Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Publication number: 20090276078
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Application
    Filed: July 10, 2009
    Publication date: November 5, 2009
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Patent number: 7596421
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: September 29, 2009
    Assignee: Kabushik Kaisha Toshiba
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Patent number: 7531462
    Abstract: A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsujiro Tanzawa, Norihiko Tsuchiya, Junji Sugamoto, Yukihiro Ushiku
  • Patent number: 7529631
    Abstract: A defect detection system includes a data acquiring section that acquires time series data of device parameter of each manufacturing device including an exposure device, and information on defect distribution in an area with a size smaller than a chip area size, a pattern classifying section that assembles the information on the defect distribution in units of shot or chip areas, and classifies the distributions to a defect pattern, a feature quantity calculating section that processes the time series data and calculates a feature quantity, a significant difference test section that calculates occurrence frequency distributions of the shot or chip area wherein the defect pattern to the feature quantity exists and does not exist, respectively, and determines the presence/absence of significant difference between the frequency distributions, and a defect detecting section that detects the device parameter corresponding to the feature quantity as the cause of defect of the defect pattern.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Yasutaka Arakawa, Junji Sugamoto
  • Publication number: 20080147226
    Abstract: A management system includes a variable-period setting unit that sets a variable period in which quality-control values vary. Then, a retrieving unit retrieves events sandwiching the variable period. The events can be a maintenance of the semiconductor manufacturing device and/or a change of a correction value. An analysis-period setting unit sets an analysis period for analyzing a cause of variation of the quality-control values between the events retrieved by the retrieving unit.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 19, 2008
    Inventors: Hiroshi MATSUSHITA, Junji Sugamoto, Masafumi Asano
  • Patent number: 7324855
    Abstract: A process-state management system encompasses: a plurality of production machines; a control server configured to collectively control at least part of the production machines; a management server including a data-linking module configured to link operation-management data of the production machines with corresponding management information transmitted from the control server, respectively, the management server analyze the operation-management data linked with the management information with a common analysis application; and a management database configured to store the operation-management data linked with the management information.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: January 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Hidenori Kakinuma, Tsutomu Miki, Junji Sugamoto, Akira Ogawa, Yoshinori Ookawauchi, Giichi Inoue, Tomomi Ino
  • Publication number: 20080004823
    Abstract: A defect detection system includes a data acquiring section that acquires time series data of device parameter of each manufacturing device including an exposure device, and information on defect distribution in an area with a size smaller than a chip area size, a pattern classifying section that assembles the information on the defect distribution in units of shot or chip areas, and classifies the distributions to a defect pattern, a feature quantity calculating section that processes the time series data and calculates a feature quantity, a significant difference test section that calculates occurrence frequency distributions of the shot or chip area wherein the defect pattern to the feature quantity exists and does not exist, respectively, and determines the presence/absence of significant difference between the frequency distributions, and a defect detecting section that detects the device parameter corresponding to the feature quantity as the cause of defect of the defect pattern.
    Type: Application
    Filed: June 19, 2007
    Publication date: January 3, 2008
    Inventors: Hiroshi Matsushita, Yasutaka Arakawa, Junji Sugamoto
  • Patent number: 7314766
    Abstract: A treatment method of a semiconductor wafer includes treating the semiconductor wafer in a first solution having at least one kind of an oxidative acid and an oxidizing agent and treating the semiconductor wafer in a second solution having at least one of HF and NH4F.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: January 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Sugamoto, Norihiko Tsuchiya, Yukihiro Ushiku, Katsujiro Tanzawa
  • Publication number: 20070276528
    Abstract: According to the present, there is proved a semiconductor fabrication apparatus management system having: a sensor which monitors and outputs a plurality of apparatus parameters of a semiconductor fabrication apparatus which fabricates a semiconductor device; a measurement unit which measures a dimensional value of the semiconductor device, and outputs the dimensional value as dimensional data; an apparatus parameter storage unit which stores the apparatus parameters; a dimensional data storage unit which stores the dimensional data; an apparatus parameter controller which calculates predicted dimensional data by extracting the dimensional data from the dimensional data storage unit, and controls at least one of the plurality of apparatus parameters on the basis of the predicted dimensional data; and an abnormality factor extraction unit which analyzes correlations between the controlled apparatus parameter and other apparatus parameters, and extracts an abnormal apparatus parameter on the basis of a calcu
    Type: Application
    Filed: March 28, 2007
    Publication date: November 29, 2007
    Inventors: Hiroshi Matsushita, Junji Sugamoto, Masafumi Asano
  • Publication number: 20070254482
    Abstract: A method for manufacturing a semiconductor device has measuring a finished state of a wafer in a completed process, estimating an in-surface tendency of the wafer based on a result of the measuring, estimating a surface characteristic of the wafer based on the estimated in-surface tendency, setting a process condition of a uncompleted process based on the estimated surface characteristic and controlling the uncompleted process based on the set process condition.
    Type: Application
    Filed: April 25, 2007
    Publication date: November 1, 2007
    Inventors: Kenji Kawabata, Junji Sugamoto
  • Publication number: 20070225853
    Abstract: A method for controlling a semiconductor manufacturing apparatus for processing wafers divided for each lot, has acquiring quality control value data group containing quality control value data of wafers in a plurality of lots previously processed, and an equipment engineering system parameter group containing equipment engineering system parameters corresponding to the wafers; creating a prediction formula of quality control value data, acquiring a first equipment engineering system parameters; inputting the first equipment engineering system parameters to the prediction formula, and performing calculation to predict first quality control value data of the wafers in the first lot; determining processing of the wafers corresponding to the first quality control value data; acquiring measured first quality control value data of the wafers in the first lot; replacing the quality control value data corresponding to the wafers in the first processed lot; updating the prediction formula.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 27, 2007
    Inventors: Hiroshi Matsushita, Junji Sugamoto, Masafumi Asano
  • Patent number: 7221991
    Abstract: A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series data by algorithms to calculate indices corresponding to the respective algorithms; an index analysis unit providing first and second frequency distributions of the indices categorized with and without the target failure pattern, to implement significance test between the first and second frequency distributions; and an abnormal parameter extraction unit extracting failure cause index of failure pattern by comparing value of the significance test with test reference value.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: May 22, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Tomonobu Noda, Kenichi Kadota, Junji Sugamoto, Yukihiro Ushiku
  • Publication number: 20060287754
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 21, 2006
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Publication number: 20060281281
    Abstract: A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 14, 2006
    Inventors: Katsujiro Tanzawa, Norihiko Tsuchiya, Junji Sugamoto, Yukihiro Ushiku