Patents by Inventor Junji Yano
Junji Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10558360Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: February 13, 2018Date of Patent: February 11, 2020Assignee: Toshiba Memory CorporationInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Publication number: 20190347016Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: ApplicationFiled: July 23, 2019Publication date: November 14, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 10379762Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: GrantFiled: August 31, 2018Date of Patent: August 13, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20190196723Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.Type: ApplicationFiled: March 5, 2019Publication date: June 27, 2019Applicant: Toshiba Memory CorporationInventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
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Publication number: 20180373447Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: ApplicationFiled: August 31, 2018Publication date: December 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
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Patent number: 10067698Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: GrantFiled: January 24, 2017Date of Patent: September 4, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20180165011Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: ApplicationFiled: February 13, 2018Publication date: June 14, 2018Applicant: Toshiba Memory CorporationInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 9933941Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: September 20, 2016Date of Patent: April 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Publication number: 20170131929Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
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Patent number: 9582370Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: GrantFiled: September 1, 2015Date of Patent: February 28, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20170010818Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
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Patent number: 9483192Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: October 26, 2015Date of Patent: November 1, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 9417799Abstract: A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.Type: GrantFiled: June 17, 2015Date of Patent: August 16, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki, Wataru Okamoto
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Patent number: 9324653Abstract: On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.Type: GrantFiled: November 20, 2013Date of Patent: April 26, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Shinichi Kanno, Junji Yano
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Patent number: 9280292Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: April 10, 2015Date of Patent: March 8, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Publication number: 20160062675Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.Type: ApplicationFiled: October 26, 2015Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
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Publication number: 20160055080Abstract: A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.Type: ApplicationFiled: November 5, 2015Publication date: February 25, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Kosuke HATSUDA, Hidenori MATSUZAKI
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Publication number: 20160041767Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: ApplicationFiled: October 26, 2015Publication date: February 11, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
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Publication number: 20160019113Abstract: A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.Type: ApplicationFiled: September 28, 2015Publication date: January 21, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira
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Publication number: 20150370646Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: ApplicationFiled: September 1, 2015Publication date: December 24, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda