Patents by Inventor Junko Sayama

Junko Sayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6289507
    Abstract: In an optimization apparatus embedded in a compiler apparatus that compiles a high-level language program to a machine language program, equivalence relations among a plurality of expressions are analyzed in a short time period by calculating an equivalent expression set group of each basic block, the equivalent expression set group being composed of equivalent expression sets with equivalence relations. Specifically, an equivalent expression set group at the entry point of a basic block is calculated from equivalent expression set groups at the exit points of basic blocks that precede the basic block, and then an equivalent expression set group at the exit point of the basic block is calculated from the equivalent expression set group at the entry point of the basic block. These calculations are repeated until there are no more changes to the equivalent expression set group at the exit point of any of the basic blocks.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: September 11, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Tanaka, Kensuke Odani, Hirohisa Tanaka, Junko Sayama
  • Patent number: 5923883
    Abstract: The basic block division unit 2 divides the instruction sequence into basic blocks which are sequences with a continuous execution order. The control flow analysis unit 3 analyzes the control flow between basic blocks. The global equivalence relation analysis unit 4 traces the control flow between basic blocks and analyzes equivalence relations between resources, such as memory and registers, which cross over between basic blocks. The code is then optimized using these equivalence relations which cross over between basic blocks. In this way, the equivalence relations between resources in the program are analyzed globally and are used in the optimization of the code, so that a greatest possible reduction can be achieved in the code size and execution time of the program.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: July 13, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirohisa Tanaka, Junko Sayama, Akira Tanaka
  • Patent number: 5881288
    Abstract: A program development system in which the debugging apparatus is informed of all of the optimization processes which have been performed. A primitive storage unit stores record information for the optimization processes. The input unit receives an input of a variable and a value, or an input of a line where execution is to be halted. The primitive combining unit obtains record information showing the optimization processes. The code execution unit executes the execution code. The variable operation unit obtains the value of a variable based on relations between variables and resources. The output unit displays the obtained value of the variable. The line display unit displays the program or the generated execution code. The line information display unit displays, in line units, information relating to the optimization performed for each line, The operation-possible variable display unit displays, for each line, variables which can be set and referred to in the line.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: March 9, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Sumi, Shuichi Takayama, Junko Sayama, Yoshiyuki Iwamura, Shoji Nagata, Motohide Nishibata
  • Patent number: 5850552
    Abstract: An optimization apparatus is provided for removing hazards from a program by rearranging instructions for each program segment. The apparatus comprises: a Directed Acyclic Graph (DAG) generating means for generating DAGs for each program segment; a hazard marking means for marking hazard-including combinations of a parent instruction and a child instruction in the DAGs for hazard; and a rearranging means for rearranging the instructions for each program segment so that instructions are inserted between the instructions of each marked combination, wherein the inserted instructions do not destroy values stored in resources used by the instructions of the marked combination.
    Type: Grant
    Filed: April 8, 1996
    Date of Patent: December 15, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kensuke Odani, Junko Sayama, Akira Tanaka
  • Patent number: 5842021
    Abstract: The definition and use information of a constant hold variable are caused to be stored in a constant hold variable information hold unit 6 by a constant hold variable definition detection unit 7 and a use expression detection unit 8. A partial constant expression rewrite unit 9 rewrites to a constant a constant hold variable which, when a variable is rewritten to a constant, allows an expression containing the variable to be convoluted into a constant. A cost judgement and rewrite unit 10 judges by a cost whether the variable is to be used with loading it in a register or constant propagation is to be conducted, and, if constant propagation is to be conducted, rewrites the variable with a constant. A resource allocation unit 11 allocates the variable to a resource. A memory variable rewrite unit 12 rewrites a constant hold variable allocated to a memory to a constant value. A constant hold variable definition removal unit 13 removes the definition of a constant hold variable which becomes unnecessary.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: November 24, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kensuke Odani, Junko Sayama, Akira Tanaka
  • Patent number: 5790862
    Abstract: A resource assigning apparatus which generates assignments which are combinations of variables and their respective live ranges, which investigates, for each assignment, other assignments with live ranges which interfere or which are continuous and which calculates assigning priority levels. Next, the assigning resource element determination unit assigns each assignment to an assignable resource element starting with the assignment with the highest priority level, in doing so taking into account the use cost which is the cost incurred by the parts of the program which use an assignment and the resource succession relations, thereby calculating a profit value which standardizes an evaluation of a reduction in transfer instructions in the object code and assigning assignments to resource elements with a lowest use cost and highest profit value. In this way, by thoroughly investigating the relations between assignments which allow assigning to a same resource element, a more optimal assigning result is attained.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: August 4, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Tanaka, Junko Sayama, Hiroshi Yukawa, Kensuke Odani
  • Patent number: 5642512
    Abstract: The present invention is constructed so as to form simple blocks within each basic block, with the simple block internal live range storage unit 12 storing variables whose live ranges are entirely located within one simple block. basic block internal live range storage unit 13 stores variables whose live ranges are located within a number of simple blocks but, at the same time, entirely within one basic block, and the inter-basic block live range group storage unit 14 stores variables whose live ranges extend between basic blocks. The live range generation unit 15 detects the live ranges of the variables and stores the result in the live range storage unit 11, whilst also storing the variables during the detection of live ranges in one of the simple block internal live range storage unit 12, the basic block internal live range storage unit 13 and the inter-basic block live range group storage unit 14.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: June 24, 1997
    Assignee: Matsushita Electric Co.
    Inventors: Akira Tanaka, Junko Sayama, Hiroshi Yukawa