Patents by Inventor Jun-Kyu Yang
Jun-Kyu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071500Abstract: Memory array structures, and methods of their formation, might include a first memory cell having a first control gate and an adjacent first portion of a charge-blocking structure, a second memory cell having a second control gate and an adjacent second portion of the charge-blocking structure, and a first dielectric material between the first control gate and the second control gate, and adjacent to a third portion of the charge-blocking structure that is between the first and second portions of the charge-blocking structure. The third portion of the charge-blocking structure might include a second dielectric material and a third dielectric material different than the second dielectric material, and the first portion of the charge-blocking structure and the second portion of the charge-blocking structure might each include the third dielectric material and a fourth dielectric material different than the second dielectric material. Apparatus might include such memory array structures.Type: ApplicationFiled: August 15, 2023Publication date: February 29, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Jae Kyu Choi, Jin Yue, Kyubong Jung, Albert Fayrushin, Jae Young Ahn, Jun Kyu Yang
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Patent number: 10720447Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: GrantFiled: July 16, 2019Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Publication number: 20190341400Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Patent number: 10411034Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: GrantFiled: June 7, 2018Date of Patent: September 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Patent number: 10355099Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.Type: GrantFiled: January 14, 2018Date of Patent: July 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Yeoung Choi, Jun Kyu Yang, Young Jin Noh, Jae Young Ahn, Jae Hyun Yang, Dong Chul Yoo, Jae Ho Choi
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Publication number: 20190157293Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: ApplicationFiled: June 7, 2018Publication date: May 23, 2019Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Publication number: 20180366554Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.Type: ApplicationFiled: January 14, 2018Publication date: December 20, 2018Inventors: Eun Yeoung CHOI, Jun Kyu YANG, Young Jin NOH, Jae Young AHN, Jae Hyun YANG, Dong Chul YOO, Jae Ho CHOI
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Patent number: 9461061Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.Type: GrantFiled: November 18, 2014Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Jin-Gyun Kim, Jae-Young Ahn, Hun Hyeong Lim, Ki-Hyun Hwang
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Patent number: 9431416Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.Type: GrantFiled: October 28, 2014Date of Patent: August 30, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-ouk Nam, Jun-kyu Yang, Hun-hyeong Lim, Ki-hyun Hwang, Jae-young Ahn, Dong-chul Yoo
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Patent number: 9276133Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.Type: GrantFiled: February 19, 2014Date of Patent: March 1, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwan Kim, Jun-Kyu Yang, Hun-Hyeong Lim, Jae-ho Choi, Ki-Hyun Hwang
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Patent number: 9240357Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.Type: GrantFiled: December 9, 2013Date of Patent: January 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Gon Kim, Jong-Hoon Kang, Jae-Young Ahn, Jun-Kyu Yang, Han-Mei Choi, Ki-Hyun Hwang
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Patent number: 9082659Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: GrantFiled: March 10, 2015Date of Patent: July 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Publication number: 20150187790Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Publication number: 20150137210Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.Type: ApplicationFiled: November 18, 2014Publication date: May 21, 2015Inventors: Phil-Ouk NAM, Jun-Kyu YANG, Jin-Gyun KIM, Jae-Young AHN, Hun Hyeong LIM, Ki-Hyun HWANG
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Publication number: 20150115348Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.Type: ApplicationFiled: October 28, 2014Publication date: April 30, 2015Inventors: Phil-ouk Nam, Jun-kyu Yang, Hun-hyeong Lim, Ki-hyun Hwang, Jae-young Ahn, Dong-chul Yoo
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Patent number: 8987805Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: GrantFiled: August 20, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Publication number: 20140332875Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.Type: ApplicationFiled: February 19, 2014Publication date: November 13, 2014Inventors: Jung-Hwan Kim, Jun-Kyu Yang, Hun-Hyeong Lim, Jae-ho Choi, Ki-Hyun Hwang
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Publication number: 20140322832Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.Type: ApplicationFiled: December 9, 2013Publication date: October 30, 2014Inventors: Tae-Gon KIM, Jong-Hoon KANG, Jae-Young AHN, Jun-Kyu YANG, Han-Mei CHOI, Ki-Hyun HWANG
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Patent number: 8748249Abstract: A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.Type: GrantFiled: April 26, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-kyu Yang, Ki-hyun Hwang, Phil-ouk Nam, Jae-young Ahn, Han-mei Choi, Dong-chul Yoo
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Publication number: 20140054676Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: ApplicationFiled: August 20, 2013Publication date: February 27, 2014Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn