Patents by Inventor Junsoo KO

Junsoo KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICES
    Publication number: 20240136396
    Abstract: A semiconductor device may include an active pattern on a substrate; an isolation pattern on the substrate, the isolation pattern covering opposite sidewalls of the active pattern; a liner on the isolation pattern, a liner including a material different from the isolation pattern; a gate structure contacting an upper surface of the active pattern and an upper surface of the liner; and a plurality of channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the plurality of channels extending through the gate structure.
    Type: Application
    Filed: April 30, 2023
    Publication date: April 25, 2024
    Inventors: Jiho Yoo, Kihyung Ko, Junsoo Kim, Hyunsup Kim, Jihoon Cha
  • Phase locked loop for reducing fractional spur noise
    Patent number: 9735788
    Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ja Yol Lee, Minjae Lee, Cheon Soo Kim, Jaehyun Kang, Junsoo Ko
  • PHASE LOCKED LOOP FOR REDUCING FRACTIONAL SPUR NOISE
    Publication number: 20160373115
    Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
    Type: Application
    Filed: June 17, 2016
    Publication date: December 22, 2016
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ja Yol LEE, Minjae LEE, Cheon Soo KIM, Jaehyun KANG, Junsoo KO