Abstract: Provided is a multimedia data stream processing method, an electronic device and a storage medium, relating to the field of artificial intelligence, and specifically, to the technical fields of cloud computing, media cloud technology, and the like, which may be applied to scenes such as smart cloud. The multimedia data stream processing method includes: allocating a plurality of sub-streams of a multimedia data stream to a plurality of edge resource nodes, where the multimedia data stream is segmented into a plurality of slices and each of the plurality of sub-streams includes a part of the plurality of slices of the multimedia data stream; and scheduling the plurality of edge resource nodes to provide the plurality of sub-streams of the multimedia data stream for a terminal device.

Abstract: A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.

Abstract: Provided is a multimedia data stream processing method, an electronic device and a storage medium, relating to the field of artificial intelligence, and specifically, to the technical fields of cloud computing, media cloud technology, and the like, which may be applied to scenes such as smart cloud. The multimedia data stream processing method includes: allocating a plurality of sub-streams of a multimedia data stream to a plurality of edge resource nodes, where the multimedia data stream is segmented into a plurality of slices and each of the plurality of sub-streams includes a part of the plurality of slices of the multimedia data stream; and scheduling the plurality of edge resource nodes to provide the plurality of sub-streams of the multimedia data stream for a terminal device.

Abstract: The application discloses a method and apparatus for spatial data processing, and relates to the technical field of data processing. One specific implementation mode of the method comprises: acquiring at least two types of spatial data sets; constructing spatial indexes for the spatial data sets; constructing spatial geometric groups in accordance with the spatial indexes and the at least two types of spatial data sets; placing the spatial geometric groups into a message queue, and subjecting the spatial geometric groups to a spatial correlation calculation by idle threads, which are threads for processing spatial data in the spatial data sets. The implementation mode can effectively balance calculation resources, reduce consumption of the calculation resources, and meanwhile improve a processing efficiency of spatial data.

Abstract: The present invention discloses a method, apparatus, device and computer-readable medium for trajectory compression, and relates to the technical field of computers. One specific implementation of the method comprises: screening, among trajectory points of a traveling trajectory, reserved trajectory points of the traveling trajectory according to deviation degrees of the trajectory points from roads; determining, in conjunction with traveling periods of the reserved trajectory points, the reserved trajectory points as key trajectory points, the traveling period being a time interval from a previous trajectory point of the reserved trajectory point to a next trajectory point of the reserved trajectory point; adding the starting point of the traveling trajectory, the key trajectory points and the ending point of the traveling trajectory to a compressed trajectory so as to compress the traveling trajectory.

Abstract: Disclosed are a vehicle guidance method, apparatus, and system for a freeway. The method includes: responsive to a detection a driving speed of a vehicle in a monitored road section is less than a preset proportion of an average driving speed of the monitored road section, determining the vehicle that the driving speed thereof is less than the preset proportion of the average driving speed as an abnormal vehicle, and determining a lane in which the abnormal vehicle is located as an abnormal lane; determining, according to an average driving speed and a traffic density of each lane in the monitored road section, whether there is a congestion risk; responsive to a determination that there is the congestion risk, obtaining a respective guidance scheme of each vehicle in each lane; and sending the respective guidance scheme to each vehicle.

Abstract: The present disclosure provides a CMOS image sensor and a method for forming the same. The method includes: forming a substrate, a plurality of photosensitive doped layers on the substrate, an isolation layer on the plurality of photosensitive doped layers, and an active layer on the isolation layer, wherein the substrate comprises a plurality of mutually discrete pixel areas, and each photosensitive doped layer is respectively disposed on each pixel area; forming an electrical device in the active layer and on the active layer; forming an interconnection structure in the isolation layer and the active layer, wherein the plurality of photosensitive doped layers are electrically coupled with the electrical device by the interconnection structure. The method can increase working areas of a photosensitive area and a reading circuit area simultaneously, thereby improving a device performance.

Abstract: A CMOS image sensor and a method for forming the CMOS image sensor are provided. The method includes: forming a substrate structure and a photosensitive doped layer, wherein the substrate structure includes a plurality of pixel regions which are mutually discrete, and the photosensitive doped layer is disposed in a pixel region; and forming a switching device on the photosensitive doped layer. The switching device is formed on the photosensitive doped layer in a stacked manner. Therefore, an area of the pixel region can be reduced and a pixel density can be improved, and a size of the photosensitive region and a size of the reading circuit can be balanced, which is conducive to obtaining better photosensitive characteristics and switching performance.

Abstract: A method for manufacturing logic device isolation in an embedded storage process, removing the pad silicon nitride and floating gate polysilicon layer in a shallow trench isolation area and retaining the floating gate oxide layer; depositing acid etching silicon nitride; removing the acid etching silicon nitride at the bottom of the shallow trench isolation and a portion of the silicon substrate adjacent to and under the shallow trench isolation, to form a trench and retain the acid etching silicon nitride on a side of the floating gate polysilicon layer close to the shallow trench isolation; remove the acid etching silicon nitride on the side of the floating gate polysilicon layer close to the shallow trench isolation.

Abstract: The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.

Abstract: A method for manufacturing logic device isolation in an embedded storage process, removing the pad silicon nitride and floating gate polysilicon layer in a shallow trench isolation area and retaining the floating gate oxide layer; depositing acid etching silicon nitride; removing the acid etching silicon nitride at the bottom of the shallow trench isolation and a portion of the silicon substrate adjacent to and under the shallow trench isolation, to form a trench and retain the acid etching silicon nitride on a side of the floating gate polysilicon layer close to the shallow trench isolation; remove the acid etching silicon nitride on the side of the floating gate polysilicon layer close to the shallow trench isolation.

Abstract: A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.

Abstract: The present application relates to the technical field of semiconductor manufacturing, in particular to a device integrated with a three-dimensional MIM capacitor and a method for manufacturing the same. The device comprising: a first dielectric layer, a first conductive metal structure being formed in the first dielectric layer; and a second dielectric layer, plurality of MIM capacitors being formed in the second dielectric layer, the bottom of each of the MIM capacitors being connected to the first conductive metal structure, and the plurality of three-dimensional MIM capacitors being arranged as array in a two-dimensional plane presented by the second dielectric layer; wherein each of the three-dimensional MIM capacitors sequentially comprises an upper electrode, a dielectric layer covering the bottom sides of the upper electrode, and a lower electrode layer covering an outer surface of the dielectric layer; the lower electrode layer is connected to the first conductive metal structure.

Abstract: A method for manufacturing a capacitor includes: forming a polysilicon layer on a substrate; forming a polysilicon structure by etching the polysilicon layer, wherein the polysilicon structure comprises a lower electrode plate of the capacitor; forming sidewalls on two sides of the polysilicon structure; depositing a dielectric layer and a conductive layer sequentially; performing a photolithography process to define salicide block layer patterns and upper electrode plate patterns of the capacitor; forming a salicide block layer, and an upper electrode plate and a dielectric layer of the capacitor, by sequentially etching the conductive layer and the dielectric layer, according to the salicide block layer patterns and the upper electrode plate patterns of the capacitor; and forming salicides.

Abstract: A method for manufacturing an LDMOS device includes: forming STI in a substrate; forming a well region in the substrate; forming a body region at one end of the well region, and forming a drift region at the other end of the well region; forming a gate dielectric layer on the substrate; forming a gate structure; forming a drain region in the drift region, and forming a source region in the body region; forming a salicide block layer, wherein the salicide block layer is composed of stacked dielectric layer and conductive layer, the salicide block layer covers the drift region between the gate structure and the drain region, and the salicide block layer extends above the gate structure; forming salicides on the tops of the drain region, the source region, and the gate structure; depositing an interlayer dielectric layer; and forming contacts in the interlayer dielectric layer.

Abstract: The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.

Abstract: The present application relates to the technical field of semiconductor manufacturing, in particular to a device integrated with a three-dimensional MIM capacitor and a method for manufacturing the same. The device comprising: a first dielectric layer, a first conductive metal structure being formed in the first dielectric layer; and a second dielectric layer, plurality of MIM capacitors being formed in the second dielectric layer, the bottom of each of the MIM capacitors being connected to the first conductive metal structure, and the plurality of three-dimensional MIM capacitors being arranged as array in a two-dimensional plane presented by the second dielectric layer; wherein each of the three-dimensional MIM capacitors sequentially comprises an upper electrode, a dielectric layer covering the bottom sides of the upper electrode, and a lower electrode layer covering an outer surface of the dielectric layer; the lower electrode layer is connected to the first conductive metal structure.

Abstract: A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.

Abstract: A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.