Abstract: The present invention aims to provide a reproduced signal evaluation method and a write adjustment method for offering a Blu-ray disc having a large storage capacity with excellent media compatibility. An evaluation index L-SEAT is calculated through signed addition using a Euclidean distance difference calculated from at least one of target signals in which a focused edge is shifted to the right and left, and the quality of the reproduced signal is evaluated based on the evaluation index. Write condition adjustment using the index enables write adjustment not depending on SNR and achieving high adjustment accuracy.

Abstract: Herein disclosed a phase difference detection apparatus for detecting a phase difference between a first signal and a second signal, which may include a waveform equalization section configured to input the first and second signals as a target waveform and an input waveform, respectively, to perform a waveform equalization process using a FIR filter so that the input waveform may coincide with the target waveform; and a phase difference detection section configured to perform a predetermined calculation based on predetermined tap coefficients of the FIR filter in the waveform equalization section to calculate an asymmetric component of the tap coefficients of the FIR filter thereby to detect the phase difference between the first and second signals.

Abstract: A reproduction signal evaluation unit has: a pattern detection section for extracting, from a binary signal, a specific state transition pattern which has a possibility of causing a bit error; a differential metric computing section for computing a differential metric based on the binary signal of the extracted state transition pattern; an error computing section for computing an error rate predicted based on an integration value that is integrated by an integration section, a count value that is counted by a pattern count section, an integration value that is integrated by another integration section, and a count value that is counted by another pattern count section, and a standard deviation computing section for computing a standard deviation based on the computed error rate.

Abstract: An evaluating device including: a Viterbi detector to perform bit detection by Viterbi detection from a reproduced signal in which bit information is reproduced; a metric difference calculator to calculate a metric difference between values of path metrics for a second path and a maximum likelihood path when at least an error pattern between the maximum likelihood path as a path surviving as a result of path selection by the Viterbi detector and the second path compared finally with the maximum likelihood path corresponds to one of a predetermined plural error patterns; and an evaluation value calculator to compare each of values of metric differences calculated by the metric difference calculator for each error pattern, with an individual threshold value obtained by dividing a Euclidean distance between the maximum likelihood path and the second path in each error pattern by a common value, and calculate a total number of values of the metric differences less than the threshold value as an evaluation value.

Abstract: A reproduction signal evaluation method for evaluating quality of a reproduction signal reproduced from an information recording medium based on a binary signal generated from the reproduction signal using a PRML signal processing system, includes: a pattern extraction step of extracting, from the binary signal, a specific state transition pattern which has the possibility of causing a bit error; a step of computing a differential metric based on the binary signal; an extraction step of extracting the differential metric which is not greater than a predetermined signal processing threshold; a step of determining a mean value of the differential metrics which are not greater than the signal processing threshold and extracted in the extraction step; a standard deviation computing step of determining a standard deviation which corresponds to an error rate predicted from the mean value; and an evaluation step of evaluating a quality of the reproduction signal using the standard deviation.

Abstract: The invention relates to a maximum likelihood decoding device that performs Partial Response Maximum Likelihood decoding on a reproduced data signal from a recording media or another source. The device includes a Viterbi detector that performs bit detection from the reproduced signal. The Viterbi device can have variable setting for branch metric calculations based on the reference levels in the reproduced signal. The device measures and attempts to reduce the Euclidean distance between a maximum likelihood path selected by the Viterbi detector and a second path.

Abstract: A reproducing apparatus includes the following elements. A reproducing head unit irradiates an optical disk with a laser beam to obtain a reproduced signal. An offset cancellation circuit cancels an offset element of the reproduced signal. An automatic gain control circuit adjusts the amplitude of the reproduced signal processed through the offset cancellation circuit. A band switching control unit detects a fingerprint period during which the reproduced signal is affected by a fingerprint on the surface of the optical disk and, for the fingerprint period, switches a frequency band in which the offset cancellation circuit and the automatic gain control circuit function to a higher frequency band than that associated with a non-fingerprint period. A decoding unit decodes the reproduced signal processed through the automatic gain control circuit to output binary data. A data reproduction processing unit performs reproduction processing on the binary data to obtain reproduced data.

Abstract: A reproducing apparatus for reproducing channel data from a recording medium using the ITR includes a reading unit reading an information signal recorded on the recording medium; a phase interpolator interpolating a phase of the information signal read on the basis of a phase error signal sent as a feedback; a first waveform equalizer equalizing a waveform of the phase-interpolated information signal while keeping the phase of the information signal fixed; a phase-error-signal generator generating the phase error signal to be sent as a feedback to the phase interpolator on the basis of the information signal whose waveform has been equalized by the first waveform equalizer; a second waveform equalizer equalizing the waveform of the phase-interpolated information signal without limiting a phase change; and a decoder generating the channel data by decoding the information signal whose waveform has been equalized by the second waveform equalizer.

Abstract: Herein disclosed a phase difference detection apparatus for detecting a phase difference between a first signal and a second signal, which may include a waveform equalization section configured to input the first and second signals as a target waveform and an input waveform, respectively, to perform a waveform equalization process using a FIR filter so that the input waveform may coincide with the target waveform; and a phase difference detection section configured to perform a predetermined calculation based on predetermined tap coefficients of the FIR filter in the waveform equalization section to calculate an asymmetric component of the tap coefficients of the FIR filter thereby to detect the phase difference between the first and second signals.

Abstract: A maximum likelihood decoding device including Viterbi detecting means performing bit detection from a reproduced signal in which bit information is reproduced, the Viterbi detecting means variably setting reference levels used for branch metric calculation according to level of the reproduced signal, Euclidean distance calculating means calculating a Euclidean distance between a maximum likelihood path as a path surviving as a result of path selection by the Viterbi detecting means and a second path compared finally with the maximum likelihood path, metric difference calculating means calculating a metric difference between a value of a path metric for the second path and a value of a path metric for the maximum likelihood path based on the reproduced signal, the maximum likelihood path, and the second path, sample average value calculating means sampling a value of the Euclidean distance between the maximum likelihood path and the second path, the Euclidean distance being calculated by the Euclidean distanc

Abstract: An evaluating device including: a Viterbi detector to perform bit detection by Viterbi detection from a reproduced signal in which bit information is reproduced; a metric difference calculator to calculate a metric difference between values of path metrics for a second path and a maximum likelihood path when at least an error pattern between the maximum likelihood path as a path surviving as a result of path selection by the Viterbi detector and the second path compared finally with the maximum likelihood path corresponds to one of a predetermined plural error patterns; and an evaluation value calculator to compare each of values of metric differences calculated by the metric difference calculator for each error pattern, with an individual threshold value obtained by dividing a Euclidean distance between the maximum likelihood path and the second path in each error pattern by a common value, and calculate a total number of values of the metric differences less than the threshold value as an evaluation value.

Abstract: A semiconductor integrated circuit includes a test pass and a test circuit that are placed on the way of the test pass so that a stage has the same excess value when the stage has different stage labels and different excess values in a scan chain of a stage interval n. A test pattern generation method for the semiconductor integrated circuit is also disclosed.

Abstract: In a semiconductor integrated circuit, a test controller generates test patterns for all of the pins of a core logic from test patterns for only the pins necessary for the test. The test controller receives information on pins to be tested and first input test patterns including input values and output expectation values for the pins to be tested. The test controller sets the input values or output expectation values of pins which are not to be tested to predetermined values and generates a second input test pattern in which the input values or output expectation values of all the pins are set. The second input pattern is provided to the core logic. An output test pattern is obtained in exactly the reverse order.

Abstract: In the semiconductor integrated circuit the test controller generates test patterns for all the pins from test patterns for only pins necessary for the test. The test controller receives information on pins to be tested and first input test patterns constructed by input values and output expectation values for the pins to be tested. The test controller sets the input values or output expectation values of pins which are not to be tested to predetermined values and thereby generates a second input test pattern in which the input values or output expectation values of all the pins are set. The second input pattern is provided to the core logic. The output test pattern is obtained in exactly the reverse order.

Abstract: In a semiconductor integrated circuit device, a clock buffer is arranged at the center of a chip by using a core I/O technique for arranging an input/output buffer at an arbitrary position. A clock is wired such that, with reference to a wire extending to a circuit in a chip which is farthest from the clock buffer and must be synchronously controlled. Wires extending to the other circuits are intentionally bypassed to make wires extending to all the circuits electrically equal to each other in length. Thus, a skew of a clock can be suppressed due to the isometric wiring.