Abstract: A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact with the first semiconductor layer through the grooves, to form a void portion between the semiconductor substrate 1 and the second semiconductor layer. By thermally oxidizing the semiconductor substrate, the second semiconductor layer and the supporting layers, an oxide film is formed in the void portion between the semiconductor substrate and the second semiconductor layer, an oxide film is formed on side walls of the semiconductor substrate in the grooves, and the supporting layers are changed into oxide films.

Abstract: A semiconductor device comprising: a semiconductor layer formed on a dielectric; a gate electrode formed on the semiconductor layer; a compound metal layer disposed on a source side in a manner to contact a body region of the semiconductor layer; and an impurity diffusion layer disposed on a drain side in a manner to contact the body region of the semiconductor layer.

Abstract: Single-crystalline silicon layers 7a and 7b are selectively formed on LDD layers 5a and 5b by an epitaxial growth method. Opening sections 10a and 10b are formed, which expose a source layer 8 and a drain layer 8b, respectively, through an interlayer dielectric film 9 and the single-crystalline silicon layers 7a and 7b, respectively, and then, plugs 12a and 12b are formed in the opening sections 10a and 10b embedded through barrier metal films 11a and 11b, respectively.

Abstract: In a CMOS-element-containing semiconductor device, the CMOS element comprises: a silicon substrate; an n-channel MOS element formed on the silicon substrate and including an n-type source/drain region, a gate oxide film and a gate electrode; a p-channel MOS element formed on the silicon substrate and including a p-type source/drain region, a gate oxide film and a gate electrode; and a gate wiring layer electrically interconnecting the gate electrode of the n-channel MOS element and the gate electrode of the p-channel MOS element with one another. The gate electrodes and/or the gate wiring layer include at least in part a metal silicide layer. The gate electrodes and the gate wiring layer contain at arbitrary region impurities consisting of a III group dopant and/or a V group dopant in a concentration of at most 3.times.10.sup.20 atoms cm.sup.-3.

Abstract: In a CMOS-element-containing semiconductor device, the CMOS element comprises: a silicon substrate; an n-channel MOS element formed on the silicon substrate and including an n-type source/drain region, a gate oxide film and a gate electrode; a p-channel MOS element formed on the silicon substrate and including a p-type source/drain region, a gate oxide film and a gate electrode; and a gate wiring layer electrically interconnecting the gate electrode of the n-channel MOS element and the gate electrode of the p-channel MOS element with one another. At least one of the p-channel MOS element gate electrode, the n-channel MOS element gate electrode and the gate wiring layer include at least in part a metal silicide layer. The gate electrodes and the gate wiring layer contain impurities consisting of at least one of a III group dopant and a V group dopant in total concentration of at most 3.times.10.sup.20 atoms cm.sup.-3.

Abstract: A semiconductor device at least including a region which contains a first impurity constituted by a group V element and a second impurity constituted by an element of high electronegativity or a halogen element such as Ti, Cl, O, Br, S, I or N in amorphous silicon, polycrystalline silicon, single crystal silicon, a refractory metal such as Ti, Mo, W, Ta, Pt, Pd and Zr or a silicide of such refractory metal. The semiconductor device is manufactured by introducing the second impurity before, after or during introduction of the first impurity, for example, by ion implantation into amorphous, polycrystalline or single crystal silicon, a refractory metal, or a silicide thereof and then annealing to form an N-type impurity region.

Abstract: In a CMOS-element-containing semiconductor device, the CMOS element comprises: a silicon substrate; an n-channel MOS element formed on the silicon substrate and including an n-type source/drain region, a gate oxide film and a gate electrode; a p-channel MOS element formed on the silicon substrate and including a p-type source/drain region, a gate oxide film and a gate electrode; and a gate wiring layer electrically interconnecting the gate electrode of the n-channel MOS element and the gate electrode of the p-channel MOS element with one another. At least one of the gate electrodes and the gate wiring layer include at least in part a metal silicide layer. The gate electrodes and the gate wiring layer contain impurities consisting of at least one of a III group dopant and a V group dopant in a total concentration of at most 3.times.10.sup.20 atoms cm.sup.-3.

Abstract: In a semiconductor device including a substrate of Si or polycrystalline silicon and an interlayer insulation film region, a region for interconnection with the substrate is composed of a refractory metal silicide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, while a region for interconnection on the interlayer insulation film on the substrate is composed of a refractory metal, or refractory metal oxide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, providing interconnections for integrated circuits. In the manufacture of this interconnection structure, rapid thermal annealing is performed at 600.degree.-1000.degree. C. on the refractory metal nitride layer of the region for interconnection with the substrate, followed by the formation of Al or Al alloy layer.

Abstract: A method of analyzing metal impurities in a surface oxide film of a semiconductor substrate enables a detection sensitivity of the order of 10.sup.11 atoms/cm.sup.2 in a simple technique. This method comprises measuring a quantity of oxide charge resulting from specified metal impurities existing in the surface oxide film formed on the surface of a semiconductor substrate, and using a predetermined correlation between the quantity of metal impurities and the quantity of oxide charge to determine the quantity of metal impurities in the surface oxide film from the measured quantity of oxide charge of the surface oxide film.

Abstract: A method of producing a semiconductor device which comprises; a first cleaning step of cleaning the surface of Si of a semiconductor device having an Si base or an Si thin film as a substrate (1) by using an APM solution; a second cleaning step of cleaning the surface of Si by using a dilute HF solution to thereby remove the uppermost surface layer (3) of a naturally oxidized film (2) formed in the first cleaning step; and a step of forming a silicon oxide film by thermally oxidizing the cleaned surface of the naturally oxidized film (2).

Abstract: In a semiconductor device including a substrate of Si or polycrystalline silicon and an interlayer insulation film region, a region for interconnection with the substrate is composed of a refractory metal silicide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, while a region for interconnection on the interlayer insulation film on the substrate is composed of a refractory metal, or refractory metal oxide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, providing interconnections for integrated circuits. In the manufacture of this interconnection structure, rapid thermal annealing is performed at 600.degree.-1000.degree. C. on the refractory metal nitride layer of the region for interconnection with the substrate, followed by the formation of Al or Al alloy layer.

Abstract: In an improved metal-oxide-semiconductor (MOS) device a polycrystalline semiconductor region is buried in a monocrystalline semiconductor substrate at the isolation region between elements of the device. A deep and narrow groove of about 1 .mu.m is formed by reactive ion etching in which the polycrystalline silicon is deposited by chemical vapor deposition. Surface polycrystalline semiconductor is removed by etching resulting in only the polycrystalline semiconductor buried in the substrate which is implanted with ions. Alternatively, polycrystalline semiconductor is deposited only in the bottom portion of the groove, ion implanted and an insulator film is formed in the remaining portion of the groove for fully isolating the polycrystalline region. Semiconductor devices prepared in accordance with the invention have flattened surfaces, reduced crystal defects and permit further miniaturization of the MOS devices.

Abstract: In an improved metal-oxide-semiconductor (MOS) device a polycrystalline semiconductor region is buried in a monocrystalline semiconductor substrate at the isolation region between elements of the device. A deep and narrow groove of about 1 .mu.m is formed by reactive ion etching in which the polycrystalline silicon is deposited by chemical vapor deposition. Surface polycrystalline semiconductor is removed by etching resulting in only the polycrystalline semiconductor buried in the substrate which is implanted with ions. Alternatively, polycrystalline semiconductor is deposited only in the bottom portion of the groove, ion implanted and an insulator film is formed in the remaining portion of the groove for fully isolating the polycrystalline region. Semiconductor devices prepared in accordance with the invention have flattened surfaces, reduced crystal defects and permit further miniaturization of the MOS devices.

Abstract: A method for forming a diffused region on a semiconductor substrate is provided. A silicide layer is formed in a region of a substrate where a diffused layer is to be formed and a material containing an impurity to be defined into the substrate deposited on the silicide layer. The device is heat treated to cause the impurity to diffuse through the silicide layer into the substrate. The method may be used to produce a MOSFET.