Patents by Inventor Jushan Xie

Jushan Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10621386
    Abstract: A method, a system and a non-transitory machine-readable storage medium are provided. In one or more aspects, a computer-implemented method for bias temperature instability (BTI) calculation of a device includes simulating the device, using an electronic design automation tool. The simulation includes determining a first degradation value after applying a first sequence of stress values to the device for a first plurality of time steps. The simulation further includes determining a first degradation recovery value after the first plurality of time steps. The simulation further includes determining a first recovered degradation value after the first plurality of time steps by combining the first degradation value and the first degradation recovery value. The first degradation value, the first degradation recovery value, and the first recovered degradation value are associated with one or more model parameters of the device.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 14, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Alvin Chen, Jushan Xie, Si-Yu Liao, Chunyi Huang, Tianlei Guo, Yanhui Li, Runsheng Wang, Shaofeng Guo, Zhuoqing Yu, Ru Huang
  • Patent number: 10223484
    Abstract: A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain and coarse grain grids in the same model group.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Donald J. O'Riordan, Richard J. O'Donovan, Saibal Saha, Jushan Xie
  • Patent number: 9411918
    Abstract: A system, method, and computer program product for extending device model parameter specification flexibility when using a subcircuit wrapper. Embodiments facilitate device modeling by allowing a modeling engineer to eliminate the explicit specification of a large set of wrapped device instance parameters as parameters to the subcircuit wrapper itself. A circuit designer may now use the subcircuit wrapper to specify an instance of the subcircuit without having to explicitly provide values for all such parameters. The simulator program's built-in device model calculates its default parameter values, which are often the result of complex expressions involving the other parameters, resulting in more accurate simulations. Subcircuit wrappers no longer need to be explicitly regenerated when a new version of the wrapped device model becomes available for the simulator (e.g., one that supports additional instance parameters that were not present on the earlier version when the subcircuit wrapper was created).
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: August 9, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: John O'Donovan, Jushan Xie, Saibal Saha
  • Patent number: 8954908
    Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: February 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Jushan Xie, Michael Tian, An-Chang Deng
  • Publication number: 20050086033
    Abstract: The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIM4 model. The device model parameters for the device model includes a plurality of base parameters, DC model parameters, temperature dependent related parameters, and AC parameters. The method also includes steps for extracting various DC model parameters. The present invention also includes a method for extracting device model parameters including the steps of extracting a portion of the DC model parameters based on the terminal current data, modifying the terminal current data based on the extracted portion of the DC model parameters, and extracting a second portion of the DC model parameters based on the modified terminal current data.
    Type: Application
    Filed: September 2, 2003
    Publication date: April 21, 2005
    Inventors: Ping Chen, Jushan Xie
  • Publication number: 20030220779
    Abstract: The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIMPD model. The method comprises obtaining terminal current data corresponding to various bias conditions in a set of test devices and extracting a portion of a plurality of DC model parameters for the device model from the terminal current data. The terminal current are then modified based on the extracted portion of the DC model parameters before extracting additional DC model parameters. The present invention also includes novel methods for extracting some of the DC model parameters.
    Type: Application
    Filed: March 31, 2003
    Publication date: November 27, 2003
    Inventors: Ping Chen, Jushan Xie
  • Patent number: 6560755
    Abstract: An exemplary method for simulating the effect of mismatch in design flows comprises receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to the netlist to obtain a modified netlist, and simulating an effect of mismatch based on the modified netlist. In one embodiment, the extracting of a mismatch model includes selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters, extracting a set of linking coefficients based on said mismatch values, and extracting said mismatch model based on said set of linking coefficients.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: May 6, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xisheng Zhang, James Chieh-Tsung Chen, Zhihong Liu, Jushan Xie, Xucheng Pang, Jingkun Fang