Patents by Inventor Justin C. Long

Justin C. Long has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bipolar transistor
    Patent number: 11916135
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: February 27, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Viorel Ontalus, Justin C. Long, Robert K. Baiocco
  • BIPOLAR TRANSISTOR
    Publication number: 20230246093
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 3, 2023
    Inventors: Viorel ONTALUS, Justin C. LONG, Robert K. BAIOCCO
  • Method to reduce resistance for a copper (Cu) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom
    Patent number: 10403574
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim Shih-Chun Liang, Atsushi Ogino, Justin C. Long
  • Method to reduce resistance for a copper (CU) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom
    Patent number: 9991202
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim S. Liang, Justin C. Long, Atsushi Ogino
  • METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
    Publication number: 20180096933
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Jim Shih-Chun Liang, Atsushi Ogino, Justin C. Long
  • METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
    Publication number: 20170005037
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Jim S. Liang, Justin C. Long, Atsushi Ogino