Abstract: Systems and methods for dynamically switching payment mechanisms for outgoing payments are disclosed. A method may include: receiving, by a payment mechanism selection computer program, a payment request from an electronic device associated with a payor to pay a payee comprising payment parameters; presenting, by the payment mechanism selection computer program, a plurality of payment features to the payor electronic device; receiving, by the payment mechanism computer program and from the payor electronic device, a selection of a subset of the plurality of payment features; determining, by the payment mechanism selection computer program, a payor payment intent from the selection of the subset of payment features; selecting, by the payment mechanism selection computer program, a payment mechanism from a plurality of available payment mechanisms that is consistent with the payor payment intent; and executing, by the payment mechanism selection computer program, the payment using the payment mechanism.

Abstract: A frequency source, such as for a wireless communications device, configured to have a duty cycle adjustment. A selected harmonic spur resulting from operation of the frequency source at one duty cycle may be avoided or minimized by operating the frequency source at a second duty cycle. Determination of the appropriate duty cycle may be based on measuring the amplitude of the harmonic spur as it appears in the output of a receive chain of the wireless device. Alternatively, the duty cycle may be set to desired value to avoid or minimize a given harmonic.

Abstract: A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

Abstract: A communication system interface between a baseband unit and a radio frequency (RF) unit is configured to advantageously use a common set of lines to carry both transmit and receive baseband analog signals between the baseband and RF unit, thereby enabling a relatively lower signal count and permitting loopback testing of elements within the baseband and the RF units.

Abstract: This disclosure includes systems and methods for frequency synthesis using a voltage-controlled oscillator (VCO) with a programmable array of capacitors. A suitable setting for the capacitor array may be derived through a non-successive iterative numerical technique. In one aspect, the iterative numerical technique may apply Newton's method to an equation relating frequency generated by the VCO and the capacitor setting of the first programmable array of capacitors. In another aspect, a secant method may be applied to determine a capacitor array setting based on previously and currently applied capacitor settings and the corresponding measured frequencies.

Abstract: A frequency source, such as for a wireless communications device, configured to have a duty cycle adjustment. A selected harmonic spur resulting from operation of the frequency source at one duty cycle may be avoided or minimized by operating the frequency source at a second duty cycle. Determination of the appropriate duty cycle may be based on measuring the amplitude of the harmonic spur as it appears in the output of a receive chain of the wireless device. Alternatively, the duty cycle may be set to desired value to avoid or minimize a given harmonic.

Abstract: A communication system interface between a baseband unit and a radio frequency (RF) unit is configured to advantageously use a common set of lines to carry both transmit and receive baseband analog signals between the baseband and RF unit, thereby enabling a relatively lower signal count and permitting loopback testing of elements within the baseband and the RF units.

Abstract: A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.

Abstract: A communication system interface between a baseband unit and a radio frequency (RF) unit is configured to advantageously use a common set of lines to carry both transmit and receive baseband analog signals between the baseband and RF unit, thereby enabling a relatively lower signal count and permitting loopback testing of elements within the baseband and the RF units.

Abstract: Electrostatic discharge (ESD) can affect the operation of and even damage an unprotected integrated circuit. Conventional ESD protection circuits may not be able to protect the integrated circuit if the voltage at the output of the integrated circuit swings with large amplitude. In some embodiments, an ESD protection circuit comprising switching circuitry that provides a low AC impedance path to ground can prevent improper triggering of the ESD protection circuit during normal operation of the integrated circuit, while ensuring that the ESD protection circuit device reliability is not compromised.

Abstract: A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

Abstract: One embodiment of the present invention sets forth a technique for mitigating fractional spurs in fractional-n frequency synthesizer circuits. The technique involves advantageously modifying certain least significant bit values in the programming bits of the fractional-n frequency synthesizer circuit to avoid pathological fractional bit patterns. As a result, fractional spurs present in conventional fractional-n frequency synthesizer circuits may be attenuated, thereby improving the overall quality of the resulting out signal.

Abstract: A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.