Abstract: A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.

Abstract: A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.

Abstract: A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.

Abstract: A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.

Abstract: A programmable layered sub-system interface includes an extension sub-layer module, a physical coding sub-layer module, a physical media attachment module, an input module, an output module, a 1st switch module and a 2nd switch module. The 1st switch module is coupled between the physical media attachment module and the physical coding sub-layer module. The 2nd switch module is operably coupled between the physical coding sub-layer module and the extension sub-layer module. The input and output modules are operably coupled to the 1st and 2nd switch modules. The 1st switch module provides various combinations of coupling between the physical media attachment module, the physical coding sub-layer module, the input module and the output module. The 2nd switch module provides combinations of coupling between the extension sub-layer module, the physical coding sub-layer module, the input module and the output module.

Abstract: A method and apparatus for managing an optical transceiver includes processing that begins by transceiving management data with modules external to the optical transceiver. The processing then continues by converting the management data transceived with the external modules between a 1st data format (e.g., MDIO interface compatible) and a generic data format (e.g., a format convenient for reading data to and writing data from a random access memory). The processing continues by transceiving management data with modules internal to the optical transceiver. The processing continues by converting the management data transceived with the internal modules between the generic data format and a 2nd data format (e.g., I2C). The processing continues by arbitrating access to a shared memory, which stores the management data in the generic format, between requests from internal modules via the second controller and requests from external modules via the first controller.

Abstract: An integrated circuit includes analog test cells to determine if an analog signal is within a predetermined voltage or current range. The test cell uses one or more analog reference signals to establish boundaries of a test range. Different embodiments of the analog test cells selectively test multiple analog signals provided in an integrated circuit. A test system can be provided to test multiple analog signals of an integrated circuit by scanning multiple analog test cells distributed throughout the integrated circuit and providing the test data for analysis. An analog circuit of an integrated circuit can be tested at different stages in manufacturing, including during a wafer stage prior to separation of individual circuit dice. Further, analog circuitry can be tested and characterized without the need for analog or digital/analog testers. In contrast, a digital only tester can be used to test analog circuitry.

Abstract: An integrated circuit includes analog test cells to determine if an analog signal is within a predetermined voltage or current range. The test cell uses one or more analog reference signals to establish boundaries of a test range. Different embodiments of the analog test cells selectively test multiple analog signals provided in an integrated circuit. A test system can be provided to test multiple analog signals of an integrated circuit by scanning multiple analog test cells distributed throughout the integrated circuit and providing the test data for analysis. An analog circuit of an integrated circuit can be tested at different stages in manufacturing, including during a wafer stage prior to separation of individual circuit dice. Further, analog circuitry can be tested and characterized without the need for analog or digital/analog testers. In contrast, a digital only tester can be used to test analog circuitry.