Abstract: Nanotwinned copper and non-nanotwinned copper may be electroplated to form mixed crystal structures such as 2-in-1 copper via and RDL structures or 2-in-1 copper via and pillar structures. Nanotwinned copper may be electroplated on a non-nanotwinned copper layer by pretreating a surface of the non-nanotwinned copper layer with an oxidizing agent or other chemical reagent. Alternatively, nanotwinned copper may be electroplated to partially fill a recess in a dielectric layer, and non-nanotwinned copper may be electroplated over the nanotwinned copper to fill the recess. Copper overburden may be subsequently removed.

Abstract: Sequential electrodeposition of metals into through-mask features on a semiconductor substrate is conducted such as to reduce the deleterious consequences of lipseal's pressure onto the mask material. In a first electroplating step, a first metal (e.g., nickel) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a first distance from the edge of the substrate. In a second electroplating step, a second metal (e.g., tin) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a greater distance from the edge of the substrate than the first distance. This allows to at least partially shift the lipseal pressure from a point that could have been damaged during the first electrodeposition step and to shield from electrolyte any cracks that might have formed in the mask material during the first electroplating step.

Abstract: In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

Abstract: A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

Abstract: Direct copper-copper bonding at low temperatures is achieved by electroplating copper features on a substrate followed by electroplanarizing the copper features. The copper features are electroplated on the substrate under conditions so that nanotwinned copper structures are formed. Electroplanarizing the copper features is performed by anodically biasing the substrate and contacting the copper features with an electrolyte so that copper is electrochemically removed. Such electrochemical removal is performed in a manner so that roughness is reduced in the copper features and substantial coplanarity is achieved among the copper features. Copper features having nanotwinned copper structures, reduced roughness, and better coplanarity enable direct copper-copper bonding at low temperatures.

Abstract: A copper structure having a high density of nanotwins is deposited on a substrate. Electroplating conditions for depositing a nanotwinned copper structure may include applying a pulsed current waveform that alternates between a constant current and no current, where a duration of no current being applied is substantially greater than a duration of a constant current being applied. In some implementations, the nanotwinned copper structure is deposited by applying a pulsed current waveform followed by a constant current waveform. In some implementations, the nanotwinned copper structure is deposited on a highly-oriented base layer, where an electroplating solution contains an accelerator additive. In some implementations, the nanotwinned copper structure is deposited on a non-copper seed layer. In some implementations, the nanotwinned copper structure is deposited at a relatively low flow rate.

Abstract: In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

Abstract: Various embodiments described herein relate to methods and apparatus for electroplating material onto a semiconductor substrate. In some cases, one or more membrane may be provided in contact with an ionically resistive element to minimize the degree to which electrolyte passes backwards from a cross flow manifold, through the ionically resistive element, and into an ionically resistive element manifold during electroplating. The membrane may be designed to route electrolyte in a desired manner in some embodiments. In these or other cases, one or more baffles may be provided in the ionically resistive element manifold to reduce the degree to which electrolyte is able to bypass the cross flow manifold by flowing back through the ionically resistive element and across the electroplating cell within the ionically resistive element manifold. These techniques can be used to improve the uniformity of electroplating results.

Abstract: Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.

Abstract: A wetting tool that provides improved wettability and debris removal from features defined by a patterned resist layer on a substrate. The substrate wetting tool relies on a wetting solution having a pH of 2.0 or less and/or a temperature ranging from 20 to 50° C. With a pH of 2.0 or less, the resist material used to form features chemically reacts, making it more hydrophilic. The wetting solution is therefore attracted into the features, beneficially reducing the chance of bubble formation and removing debris. At elevated temperatures, the heated wetting solution improves particle de-lamination and aids in dissolving debris and oxides from the substrate surface.

Abstract: Various embodiments described herein relate to methods and apparatus for electroplating material onto a semiconductor substrate. In some cases, one or more membrane may be provided in contact with an ionically resistive element to minimize the degree to which electrolyte passes backwards from a cross flow manifold, through the ionically resistive element, and into an ionically resistive element manifold during electroplating. The membrane may be designed to route electrolyte in a desired manner in some embodiments. In these or other cases, one or more baffles may be provided in the ionically resistive element manifold to reduce the degree to which electrolyte is able to bypass the cross flow manifold by flowing back through the ionically resistive element and across the electroplating cell within the ionically resistive element manifold. These techniques can be used to improve the uniformity of electroplating results.

Abstract: Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.