Abstract: An apparatus can include a processor; a controller; a data bus connector; a multiplexer operatively coupled to the data bus connector where the multiplexer includes a controller coupled state operatively coupled to the controller and a processor coupled state operatively coupled to the processor; and circuitry that responds to a signal received via the data bus connector to determine the coupled state of the multiplexer as being one of the controller coupled state and the processor coupled state. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: In one aspect, a device includes at least one processor, storage, a power supply unit (PSU) interlace which connects to a PSU and receives power from the PSU, and a power module (PM) including a power in interface for receiving power from at least one computer and a power out interface for providing power to at least one computer.

Abstract: In one aspect, a device includes at least one processor, storage, a power supply unit (PSU) interlace which connects to a PSU and receives power from the PSU, and a power module (PM) including a power in interface for receiving power from at least one computer and a power out interface for providing power to at least one computer.

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract: An apparatus can include a processor; a controller; a data bus connector; a multiplexer operatively coupled to the data bus connector where the multiplexer includes a controller coupled state operatively coupled to the controller and a processor coupled state operatively coupled to the processor; and circuitry that responds to a signal received via the data bus connector to determine the coupled state of the multiplexer as being one of the controller coupled state and the processor coupled state. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: Power supply to system resources is managed by implementing a hardware hook. System resources that should be reconfigured for an application workload are identified. A present power profile in a non-volatile memory is then updated. The present power profile is updated according to the application workload. During a system restart, the present power profile is retrieved from the non-volatile memory. Power is applied to system resources through the hardware hook based on the present power profile.

Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Abstract: According to one embodiment, an apparatus has first and second connectors configured for removably connecting to one another. The first connector circuit has a first differential amplifier, a first differential signal path, a first capacitor section capacitively coupling the first differential amplifier to the first differential signal path, and a first DC biasing circuit for imparting a first DC bias to the first differential signal path opposite the first capacitor section. The second connector circuit has a second differential amplifier, a second differential signal path, a second capacitor section capacitively coupling the second differential amplifier to the second differential signal path, and a second DC biasing circuit for imparting a second DC bias to the second differential signal path opposite the second capacitor section having a different magnitude than the first DC bias when the first and second connector are not connected.

Abstract: This invention enables authenticated communications (transactions) to take place on a standard I2C bus without requiring modification of existing I2C devices. Read and write transactions occurring on the bus are authenticated using an Authentication Agent and a shared secret key. In addition to allowing verification of the legitimacy of the transactions, the authentication of the I2C transactions enhances the reliability and serviceability of the bus and devices on the bus by allowing the Baseboard Management Controller (BMC) to quickly determine and pinpoint errors.

Abstract: Power supply to system resources is managed by implementing a hardware hook. System resources that should be reconfigured for an application workload are identified. A present power profile in a non-volatile memory is then updated. The present power profile is updated according to the application workload. During a system restart, the present power profile is retrieved from the non-volatile memory. Power is applied to system resources through the hardware hook based on the present power profile.

Abstract: A system and method are used for electronically detecting the accumulation of dust within a computer system using a capacitive dust sensor. The dust detection system may be implemented on a smaller computer, such as an individual PC, or in a more expansive system, such as a rack-based server system (“rack system”) having multiple servers and other hardware devices. In one embodiment, each server in a rack system includes a capacitive sensor responsive to the accumulation of dust. The capacitive sensor may include one or more capacitive plates integral with a heatsink. As dust collects on the capacitive plates, the capacitance increases. When a capacitance setpoint is reached, indicating the dust has reached a critical level, an alert is generated. The alerts may be received by a management console for the attention of a system administrator. Each alert may contain the identity of the server generating the alert, so that the system administrator knows which server(s) are to be removed for cleaning.

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract: According to one embodiment, an apparatus has first and second connectors configured for removably connecting to one another. The first connector circuit has a first differential amplifier, a first differential signal path, a first capacitor section capacitively coupling the first differential amplifier to the first differential signal path, and a first DC biasing circuit for imparting a first DC bias to the first differential signal path opposite the first capacitor section. The second connector circuit has a second differential amplifier, a second differential signal path, a second capacitor section capacitively coupling the second differential amplifier to the second differential signal path, and a second DC biasing circuit for imparting a second DC bias to the second differential signal path opposite the second capacitor section having a different magnitude than the first DC bias when the first and second connector are not connected.

Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Abstract: A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (Vref—test) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.

Abstract: Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered.

Abstract: Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered.

Abstract: A system and method are used for electronically detecting the accumulation of dust within a computer system using a capacitive dust sensor. The dust detection system may be implemented on a smaller computer, such as an individual PC, or in a more expansive system, such as a rack-based server system (“rack system”) having multiple servers and other hardware devices. In one embodiment, each server in a rack system includes a capacitive sensor responsive to the accumulation of dust. The capacitive sensor may include one or more capacitive plates integral with a heatsink. As dust collects on the capacitive plates, the capacitance increases. When a capacitance setpoint is reached, indicating the dust has reached a critical level, an alert is generated. The alerts may be received by a management console for the attention of a system administrator. Each alert may contain the identity of the server generating the alert, so that the system administrator knows which server(s) are to be removed for cleaning.

Abstract: A system and method for electronically detecting the accumulation of dust within a computer system using a capacitive dust sensor. The dust detection system may be implemented on a smaller computer, such as an individual PC, or in a more expansive system, such as a rack-based server system (“rack system”) having multiple servers and other hardware devices. In one embodiment, each server in a rack system includes a capacitive sensor responsive to the accumulation of dust. The capacitive sensor may include one or more capacitive plates integral with a heatsink. As dust collects on the capacitive plates, the capacitance increases. When a capacitance setpoint is reached, indicating the dust has reached a critical level, an alert is generated. The alerts may be received by a management console for the attention of a system administrator. Each alert may contain the identity of the server generating the alert, so that the system administrator knows which server(s) are to be removed for cleaning.

Abstract: Airflow control and dust removal systems and methods are disclosed. In one embodiment, a plurality of blade servers is mounted in a chassis. A blower generates airflow through the chassis. Air enters the chassis uniformly across the blade servers and flows in parallel through the servers. An airflow directing mechanism is provided for allowing airflow through a selected one of the blade servers while reducing or closing airflow to the other blade servers, to individually clean and remove dust from the selected blade server. The airflow directing mechanism may include a movable vane actuated by a rotary or linear solenoid to selectively block airflow ports of the servers. The vane may be held in a closed position, assisted by an electromagnet. The airflow directing mechanism may alternatively comprise a rolled shade having a pattern of openings. The position of the rolled shade may be controlled to align openings in the shade with airflow ports in the servers, to control which servers airflow may pass through.