Abstract: Disclosed is a communications measurement matrix display for a protocol analyzer which is used to monitor traffic on a packet-switched network. The display allows the protocol analyser user to see, at a glance, a complete and accurate overview of communications between more than thirty-one nodes on a packet-switched network, over a user selectable range of measurement-time intervals. The matrix display has two modes. One mode shows the source versus the destination nodes of the network as a 32-.times.-32 two-dimensional X-Y grid matrix having thirty one source nodes ordinally indicated along one grid axis and thirty one destination nodes ordinally indicated along the other grid axis. The thirty second ordinal position on each axis designates any nodes other than the first thirty one nodes. A display marker postioned on the grid indicates communication between the source node and the destination node which correspond to the (X,Y), that is, the (SOURCE, DESTINATION), coordinates of the marker.

Abstract: A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals. A like number of clock detection circuits each responds separately to the values of separate clock signals by producing separate qualified clock signals, each of the like number of which represents the simultaneous occurrence of a preselected transition in each particular clock signal and of a qualifier pattern signal associated with that clock signal. The several separate qualified clock signals generally occur at separate times, and each is used to individually capture into several temporary storage registers separate collections of data signal values occurring at those separate times.

Abstract: Clock signals, data words and qualifier signals are received via monitor probes during a data acquisition mode, selected data words being stored in a memory in response to the clock and qualifier signals. The stored data words may then be displayed in a tabular or a map format on a cathode ray tube screen. Data words may be acquired randomly, i.e., in a free-running sampling mode, or acquired selectively by using pattern recognition and delay trigger circuits. Using the tabular display format, data words are displayed as ones and zeroes. Using the map display format, each data word thus acquired is displayed on the CRT screen as a dot during a subsequent display mode. The position of each dot on the CRT screen uniquely identifies its address or state value. The most significant bits determine the vertical position on the CRT screen and the least significant bits determine the horizontal position of the dot. The intensity of the dot indicates the relative frequency of occurrence of that logic state.

Abstract: Clock signals, data words and qualifier signals are received via monitor probes during a data acquisition mode, selected data words being stored in a memory in response to the clock and qualifier signals. The stored data words may then be displayed in a tabular or a map format on a cathode ray tube screen. Data words may be acquired randomly, i.e., in a free-running sampling mode, or acquired selectively by using pattern recognition and delay trigger circuits. Using the tabular display format, data words are displayed as ones and zeroes. Using the map display format, each data word thus acquired is displayed on the CRT screen as a dot during a subsequent display mode. The position of each dot on the CRT screen uniquely identifies its address or state value. The most significant bits determine the vertical position on the CRT screen and the least significant bits determine the horizontal position of the dot. The intensity of the dot indicates the relative frequency of occurrence of that logic state.