Patents by Inventor Justin Sandford

Justin Sandford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070262399
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced or eliminated oxide layer beneath the high-k gate dielectric layer. A spacer adjacent a gate stack may act as an oxygen barrier to prevent the oxide from forming.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 15, 2007
    Inventors: Gilbert Dewey, Justin Sandford, Nancy Zelick, Jack Kavalieros, Suman Datta
  • Publication number: 20070126067
    Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.
    Type: Application
    Filed: December 1, 2005
    Publication date: June 7, 2007
    Inventors: Michael Hattendorf, Justin Brask, Justin Sandford, Jack Kavalieros, Matthew Metz
  • Publication number: 20060286807
    Abstract: Embodiments relate to a substrate or wafer edge support having an emmisivity greater than that of a silicon wafer, where the edge support is for supporting a wafer during processing to form circuit devices on or in the wafer. Embodiments also include temperature sensors, heat conducting gas jets, and photonic energy can be directed to sense and control the temperature of the edge support and/or wafer edge during annealing to reduce temperature roll-off or roll-up at the edge as compared to the center of the wafer. Specifically, use of an edge support having an emmisivity greater than or equal to that of the wafer during processing allows helium gas jets directed at the edge support and/or wafer edge to reduce temperature roll-up at the edge during annealing. Because wafers from different processes and anneal locations may all have different emmisivities, use of the feedback loop will enable one edge ring to support the uniform anneal of wafers with a range of different emmisivities.
    Type: Application
    Filed: June 16, 2005
    Publication date: December 21, 2006
    Inventors: Jack Hwang, Robert James, Eric Lambert, Jonathan Leonard, Richard Brindos, Karson Knutson, Mark Armstrong, Justin Sandford
  • Publication number: 20060004493
    Abstract: Embodiments relate to a substrate or wafer edge support having an emmisivity greater than that of a silicon wafer, where the edge support is for supporting a wafer during processing to form circuit devices on or in the wafer. Embodiments also include temperature sensors, heat conducting gas jets, and photonic energy can be directed to sense and control the temperature of the edge support and/or wafer edge during annealing to reduce temperature roll-off or roll-up at the edge as compared to the center of the wafer. Specifically, use of an edge support having an emmisivity greater than or equal to that of the wafer during processing allows helium gas jets directed at the edge support and/or wafer edge to reduce temperature roll-up at the edge during annealing. Because wafers from different processes and anneal locations may all have different emmisivities, use of the feedback loop will enable one edge ring to support the uniform anneal of wafers with a range of different emmisivities.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Jack Hwang, Robert James, Eric Lambert, Jonathan Leonard, Richard Brindos, Karson Knutson, Mark Armstrong, Justin Sandford
  • Patent number: 6121100
    Abstract: A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: September 19, 2000
    Assignee: Intel Corporation
    Inventors: Ebrahim Andideh, Lawrence Brigham, Robert S. Chau, Tahir Ghani, Chia-Hong Jan, Justin Sandford, Mitchell C. Taylor