Patents by Inventor Justin Weber
Justin Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105854Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.Type: ApplicationFiled: December 4, 2023Publication date: March 28, 2024Applicant: Intel CorporationInventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
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Patent number: 11843058Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.Type: GrantFiled: November 1, 2021Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
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Patent number: 11637185Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.Type: GrantFiled: September 25, 2018Date of Patent: April 25, 2023Assignee: Intel CorporationInventors: Justin Weber, Harold Kennel, Abhishek Sharma, Christopher Jezewski, Matthew V. Metz, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Van H. Le, Arnab Sen Gupta
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Patent number: 11522060Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.Type: GrantFiled: September 26, 2018Date of Patent: December 6, 2022Assignee: Intel CorporationInventors: Seung Hoon Sung, Justin Weber, Matthew Metz, Arnab Sen Gupta, Abhishek Sharma, Benjamin Chu-Kung, Gilbert Dewey, Charles Kuo, Nazila Haratipour, Shriram Shivaraman, Van H. Le, Tahir Ghani, Jack T. Kavalieros, Sean Ma
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Patent number: 11462568Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.Type: GrantFiled: June 22, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Justin Weber, Harold Kennel, Willy Rachmady, Gilbert Dewey, Van H. Le, Abhishek Sharma, Patrick Morrow, Ashish Agrawal
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Patent number: 11398560Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.Type: GrantFiled: September 26, 2018Date of Patent: July 26, 2022Assignee: Intel CorporationInventors: Gilbert Dewey, Van H. Le, Abhishek Sharma, Jack T. Kavalieros, Sean Ma, Seung Hoon Sung, Nazila Haratipour, Tahir Ghani, Justin Weber, Shriram Shivaraman
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Publication number: 20220199839Abstract: Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Arnab SEN GUPTA, Urusa ALAAN, Justin WEBER, Charles C. KUO, Yu-Jin CHEN, Kaan OGUZ, Matthew V. METZ, Abhishek A. SHARMA, Prashant MAJHI, Brian S. DOYLE, Van H. LE
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Patent number: 11365071Abstract: A material conveying system, comprising: one or more material sources for providing material to be transferred; one or more destination locations for receiving material from the one or more material sources; one or more material conveying lines; one or more vacuum pumps wherein each vacuum pump is operatively connected to one or more of the one or more destination locations via one or more vacuum source lines; a sensor disposed on, in or near each of the one or more material conveying lines; a programmable electronic control unit (ECU) connected, via wires or wirelessly, to each component of the material conveying system including the one or more material sources, the one or more destination locations, the one or more vacuum pumps and to the one or more sensors; wherein the ECU uses data from the one or more sensors to (i) determine flow patterns and/or stream density of the material being conveyed through the one or more material conveying lines; and (ii) make automatic adjustments for optimizing and maintaiType: GrantFiled: April 28, 2021Date of Patent: June 21, 2022Assignee: IPEG, IncInventors: Doug Brewster, Rich Shaffer, Max Rayburg, Justin Weber, Mike Nguyen
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Patent number: 11362189Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first conductive layer over a substrate, a first transistor having first interconnects in the first conductive layer, and a second conductive layer on an insulating layer that is on the first conductive layer. The transistor device also includes a second transistor having second interconnects in the second conductive layer, and a gate electrode over the substrate, where the gate electrode has a workfunction metal that surrounds the first and second interconnects. The first and second conductive layers may include conductive materials such as an epitaxial (EPI) layer, a metal layer, or a doped-semiconductor layer. The transistor device may further include a dielectric surrounding the interconnects as the dielectric is surrounded with the workfunction metal, and a transition layer disposed between the dielectric and interconnects. The dielectric may include a high-k dielectric material.Type: GrantFiled: September 27, 2018Date of Patent: June 14, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey, Justin Weber
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Publication number: 20220059702Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Applicant: Intel CorporationInventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
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Publication number: 20220052200Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.Type: ApplicationFiled: November 1, 2021Publication date: February 17, 2022Applicant: Intel CorporationInventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
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Patent number: 11171243Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.Type: GrantFiled: June 27, 2019Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
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Patent number: 11171239Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.Type: GrantFiled: September 13, 2019Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
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Publication number: 20210331877Abstract: A material conveying system, comprising: one or more material sources for providing material to be transferred; one or more destination locations for receiving material from the one or more material sources; one or more material conveying lines; one or more vacuum pumps wherein each vacuum pump is operatively connected to one or more of the one or more destination locations via one or more vacuum source lines; a sensor disposed on, in or near each of the one or more material conveying lines; a programmable electronic control unit (ECU) connected, via wires or wirelessly, to each component of the material conveying system including the one or more material sources, the one or more destination locations, the one or more vacuum pumps and to the one or more sensors; wherein the ECU uses data from the one or more sensors to (i) determine flow patterns and/or stream density of the material being conveyed through the one or more material conveying lines; and (ii) make automatic adjustments for optimizing and maintaiType: ApplicationFiled: April 28, 2021Publication date: October 28, 2021Inventors: Doug Brewster, Rich Shaffer, Max Rayburg, Justin Weber, Mike Nguyen
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Publication number: 20210083122Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.Type: ApplicationFiled: September 13, 2019Publication date: March 18, 2021Applicant: Intel CorporationInventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
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Publication number: 20200411692Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Applicant: Intel CorporationInventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
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Publication number: 20200105891Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first conductive layer over a substrate, a first transistor having first interconnects in the first conductive layer, and a second conductive layer on an insulating layer that is on the first conductive layer. The transistor device also includes a second transistor having second interconnects in the second conductive layer, and a gate electrode over the substrate, where the gate electrode has a workfunction metal that surrounds the first and second interconnects. The first and second conductive layers may include conductive materials such as an epitaxial (EPI) layer, a metal layer, or a doped-semiconductor layer. The transistor device may further include a dielectric surrounding the interconnects as the dielectric is surrounded with the workfunction metal, and a transition layer disposed between the dielectric and interconnects. The dielectric may include a high-k dielectric material.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Inventors: Aaron LILAK, Willy RACHMADY, Rishabh MEHANDRU, Gilbert DEWEY, Justin WEBER
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Publication number: 20200098887Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Gilbert DEWEY, Van H. LE, Abhishek SHARMA, Jack T. KAVALIEROS, Sean MA, Seung Hoon SUNG, Nazila HARATIPOUR, Tahir GHANI, Justin WEBER, Shriram SHIVARAMAN
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Publication number: 20200098875Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Seung Hoon SUNG, Justin WEBER, Matthew METZ, Arnab SEN GUPTA, Abhishek SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Charles KUO, Nazila HARATIPOUR, Shriram SHIVARAMAN, Van H. LE, Tahir GHANI, Jack T. KAVALIEROS, Sean MA
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Publication number: 20200098874Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: Justin WEBER, Harold KENNEL, Abhishek SHARMA, Christopher JEZEWSKI, Matthew V. METZ, Tahir GHANI, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Van H. LE, Arnab SEN GUPTA