Patents by Inventor Jyh-Chyurn Guo
Jyh-Chyurn Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10345371Abstract: A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.Type: GrantFiled: November 15, 2016Date of Patent: July 9, 2019Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Jyh-Chyurn Guo, Yen-Ying Lin
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Publication number: 20170242065Abstract: A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.Type: ApplicationFiled: November 15, 2016Publication date: August 24, 2017Inventors: Jyh-Chyurn GUO, Yen-Ying LIN
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Patent number: 8691599Abstract: A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capType: GrantFiled: July 27, 2011Date of Patent: April 8, 2014Assignee: National Chiao Tung UniversityInventors: Jyh-Chyurn Guo, Kuo-Liang Yeh
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Publication number: 20120197593Abstract: A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capType: ApplicationFiled: July 27, 2011Publication date: August 2, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Jyh-Chyurn Guo, Kuo-Liang Yeh
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Patent number: 7071478Abstract: A method and system is disclosed for directing charged particles on predetermined areas on a target semiconductor substrate. After aligning a wafer mask with a semiconductor wafer, with the wafer mask having one or more mask patterns thereon, the charged particles are directed to pass through the mask patterns to land on one or more selected areas on the semiconductor wafer.Type: GrantFiled: April 2, 2004Date of Patent: July 4, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen Chin Lin, Denny Tang, Li-shyue Lai, John Chern, Jyh-Chyurn Guo, Wan-Yih Lien
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Publication number: 20050218346Abstract: A method and system is disclosed for directing charged particles on predetermined areas on a target semiconductor substrate. After aligning a wafer mask with a semiconductor wafer, with the wafer mask having one or more mask patterns thereon, the charged particles are directed to pass through the mask patterns to land on one or more selected areas on the semiconductor wafer.Type: ApplicationFiled: April 2, 2004Publication date: October 6, 2005Inventors: Wen Lin, Denny Tang, Li-shyue Lai, John Chern, Jyh-Chyurn Guo, Wan-Yih Lien
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Publication number: 20050156156Abstract: Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.Type: ApplicationFiled: January 10, 2005Publication date: July 21, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Horng-Huei Tseng, Jyh-Chyurn Guo, Chenming Hu, Da-Chi Lin
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Patent number: 6894357Abstract: A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.Type: GrantFiled: June 16, 2003Date of Patent: May 17, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Jyh-Chyurn Guo
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Patent number: 6888063Abstract: Disclosed is a semiconductor radio frequency (RF) device having a shielding structure for minimizing coupling between RF passive components and conductive routing for active components. In one example, the device includes at least one shielding layer formed between the RF passive components and conductive routing. The shielding layer includes at least one opening. In another example, a second shielding layer may be used. The second shielding layer may also have an opening, and the openings in the first and second shielding layers may be offset from one another. The first and second shielding layers may be connected to each other through a guard ring, and may also be connected to a common voltage potential.Type: GrantFiled: April 14, 2004Date of Patent: May 3, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wai-Yi Lien, Chung-Long Chang, Jyh-Chyurn Guo, John Chern
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Publication number: 20050082075Abstract: Disclosed is a semiconductor radio frequency (RF) device having a shielding structure for minimizing coupling between RF passive components and conductive routing for active components. In one example, the device includes at least one shielding layer formed between the RF passive components and conductive routing. The shielding layer includes at least one opening. In another example, a second shielding layer may be used. The second shielding layer may also have an opening, and the openings in the first and second shielding layers may be offset from one another. The first and second shielding layers may be connected to each other through a guard ring, and may also be connected to a common voltage potential.Type: ApplicationFiled: April 14, 2004Publication date: April 21, 2005Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wai-Yi Lien, Chung-Long Chang, Jyh-Chyurn Guo, John Chern
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Patent number: 6878583Abstract: A new process integration method is described to form heavily doped p+ source and drain regions in a CMOS device. After defining the p- and n-well regions on a semiconductor substrate, gate silicon dioxide is deposited and nitrided in a nitrogen-containing atmosphere. Poly-silicon is then deposited and the two NMOS and PMOS gates are formed. For the p+ doping of the poly-silicon gate and S/D regions around the PMOS gate, B+ ions are then implanted. Cap dielectric layer comprising silicon dioxide is then deposited, followed by dopant activation with high temperature rapid thermal annealing. The cap dielectric layer is then used as resist protective film; it is removed from those areas of the chip that would require formation of electrical contacts. Silicide electrical contacts are then formed in these areas.Type: GrantFiled: February 5, 2003Date of Patent: April 12, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Jyh Chyurn Guo
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Patent number: 6878964Abstract: A tester for a semiconductor device is provided, which includes a bottom ground pad structure, an intermediate ground pad structure, and a top layer. The bottom ground pad structure is electrically connected to a substrate. The bottom ground pad structure includes a bottom signal shield plate. The intermediate ground pad structure is electrically connected to the bottom ground pad structure. The intermediate ground pad structure is located over the bottom ground pad structure. The top layer is located over the intermediate ground pad structure. The top layer includes a device under test (DUT), a ground probe pad, a signal probe pad, and leads. The DUT is electrically connected to the ground probe pad and the signal probe pad via the leads. The ground probe pad is electrically connected to the intermediate ground pad structure. The signal probe pad is located over the bottom signal shield plate.Type: GrantFiled: September 26, 2003Date of Patent: April 12, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wai-Yi Lien, Jyh-Chyurn Guo
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Publication number: 20050067616Abstract: A tester for a semiconductor device is provided, which includes a bottom ground pad structure, an intermediate ground pad structure, and a top layer. The bottom ground pad structure is electrically connected to a substrate. The bottom ground pad structure includes a bottom signal shield plate. The intermediate ground pad structure is electrically connected to the bottom ground pad structure. The intermediate ground pad structure is located over the bottom ground pad structure. The top layer is located over the intermediate ground pad structure. The top layer includes a device under test (DUT), a ground probe pad, a signal probe pad, and leads. The DUT is electrically connected to the ground probe pad and the signal probe pad via the leads. The ground probe pad is electrically connected to the intermediate ground pad structure. The signal probe pad is located over the bottom signal shield plate.Type: ApplicationFiled: September 26, 2003Publication date: March 31, 2005Inventors: Wai-Yi Lien, Jyh-Chyurn Guo
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Patent number: 6847098Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.Type: GrantFiled: August 14, 2003Date of Patent: January 25, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Horng-Huei Tseng, Jyh-Chyurn Guo, Chenming Hu, Da-Chi Lin
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Patent number: 6835622Abstract: Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.Type: GrantFiled: June 4, 2002Date of Patent: December 28, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Ling-Yen Yeh, Jyh-Chyurn Guo, Ih-Chin Chen
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Publication number: 20040152253Abstract: A new process integration method is described to form heavily doped p+ source and drain regions in a CMOS device. After defining the p- and n-well regions on a semiconductor substrate, gate silicon dioxide is deposited and nitrided in a nitrogen-containing atmosphere. Poly-silicon is then deposited and the two NMOS and PMOS gates are formed. For the p+ doping of the poly-silicon gate and S/D regions around the PMOS gate, B+ ions are then implanted. Cap dielectric layer comprising silicon dioxide is then deposited, followed by dopant activation with high temperature rapid thermal annealing. The cap dielectric layer is then used as resist protective film; it is removed from those areas of the chip that would require formation of electrical contacts. Silicide electrical contacts are then formed in these areas.Type: ApplicationFiled: February 5, 2003Publication date: August 5, 2004Applicant: Taiwan Semiconductor Manufacturing CompanyInventor: Jyh Chyurn Guo
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Publication number: 20030232473Abstract: Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.Type: ApplicationFiled: June 4, 2002Publication date: December 18, 2003Applicant: Taiwn Semiconductor Manufacturing Co., Ltd.Inventors: Ling-Yen Yeh, Jyh-Chyurn Guo, Ih-Chin Chen
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Patent number: 6660635Abstract: A method of cleaning a substrate before and after an LDD implantation comprising the following sequential steps. A substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH4OH. An LDD implantation is performed into the substrate to form LDD implants. The substrate is cleaned by a wet clean process excluding NH4OH.Type: GrantFiled: March 20, 2002Date of Patent: December 9, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jyh-Chyurn Guo, Wu-Der Wang
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Publication number: 20030211684Abstract: A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.Type: ApplicationFiled: June 16, 2003Publication date: November 13, 2003Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventor: Jyh-Chyurn Guo
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Patent number: 6627515Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.Type: GrantFiled: December 13, 2002Date of Patent: September 30, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Horng-Huei Tseng, Jyh-Chyurn Guo, Chenming Hu, Da-Chi Lin