Patents by Inventor Jyh-Feng Lin

Jyh-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6613592
    Abstract: A new method is provided to monitor and to prevent IMD oxide irregularities such as IMD oxide cracks. A monitoring pattern is inserted in the test line of the fabrication substrate to monitor the strength of the created layer of IMD oxide. Variations in the characteristics of the created layer of IMD oxide can in this manner be detected. In addition, design rules are provided that are aimed at avoiding layers of IMD oxide that have proven or are known to be particularly prone to the occurrence of IMD oxide cracks.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 2, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shin-Kai Chen, Chun-Chen Yeh, Jyh-Feng Lin
  • Patent number: 6369428
    Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: April 9, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Feng Lin, Kwan-Jen Chu, Yi-Pin Shen, Jer-Yuan Sheu
  • Publication number: 20010010937
    Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.
    Type: Application
    Filed: March 13, 2001
    Publication date: August 2, 2001
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Jyh-Feng Lin, Kwan-Jen Chu, Yi-Pin Shen, Jer-Yuan Sheu
  • Patent number: 6238993
    Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: May 29, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Feng Lin, Kwan-Jen Chu, Yi-Pin Shen, Jer-Yuan Sheu
  • Patent number: 6040223
    Abstract: A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO.sub.2 stress-release layer is deposited having a trapezoidal shape. A Si.sub.3 N.sub.4 layer is deposited and plasma etched back using the SiO.sub.2 layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO.sub.2 layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si.sub.3 N.sub.4 also extends over the SiO.sub.2 layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO.sub.2 along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: March 21, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Meng-Chang Liu, Jyh-Feng Lin, Ming-Shu Yen, Su-Ying Su, Fu-Ying Chiu, Chien-Hung Lin
  • Patent number: 5956566
    Abstract: A method and test site for monitoring the extent of buried contact trench formation in MOS FET integrated circuit wafers is described. A number of doped silicon parallel first test electrodes are formed in test site regions of a wafer and connected in series. The test site regions are located in the spaces between chip regions of the wafer. A layer of gate oxide is then deposited over the wafer. Test openings over the first test electrodes and buried contact openings are etched in the gate oxide layer at the same time. The test openings have the same size and shape as the buried contact openings. After polysilicon and metal silicide is deposited a photoresist mask is formed to etch the buried contact electrodes, the gate electrodes, and second test electrodes which are located directly above the test openings. Any misalignment in the photoresist mask will cause trenches to be formed in the first test electrodes as well as the formation of buried contact trenches.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: September 21, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyh-Feng Lin, Hon-Hung Lui, Yi-Te Chen
  • Patent number: 5917215
    Abstract: The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: June 29, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Kuen-Joung Chuang, Ming-Chih Chung, Jyh-Feng Lin
  • Patent number: 5915178
    Abstract: A process for fabricating a flash EEPROM device, incorporating a shallow, heavily doped, source side region, used to improve the endurance of the flash EEPROM device, has been developed. The process features placing a shallow, ion implanted arsenic region, in the semiconductor substrate, adjacent to one side of a floating gate structure, prior to creation of the control gate structure. The addition of the shallow, ion implanted arsenic region, improves the coupling ratio at the source, which in turn results in the ability of the flash EEPROM device to sustain about 1,000,000 program/erase cycles, compared to counterparts, fabricated without the shallow, source side region, only able to sustain about 400,000 program/erase cycles.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: June 22, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Min Chiang, Long-Shang Juang, Chi-Shiang Lee, Jyh-Feng Lin
  • Patent number: 5895240
    Abstract: The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: April 20, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuen-Joung Chuang, Ming-Chih Chung, Jyh-Feng Lin
  • Patent number: 5481122
    Abstract: A surface emitting AlGaInP LED having an ITO layer as a window layer to eliminate the current crowding effect, and an ohmic contact layer between its double hetero-structure of AlGaInP and the ITO layer, so that ITO can be utilized with the double hetero-structure of AlGaInP.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: January 2, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Jiunn Jou, Chuan-Ming Chang, Biing-Jye Lee, Jyh-Feng Lin
  • Patent number: RE35665
    Abstract: A surface emitting AlGaInP LED having an ITO layer as a window layer to eliminate the current crowding effect, and an ohmic contact layer between its double hereto-structure of AlGaInP and the ITO layer, so that ITO can be utilized with the double hereto-structure of AlGaInP.
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: November 18, 1997
    Assignee: Industrial Technology Research Institute
    Inventors: Jyh-Feng Lin, Chuan-Ming Chang, Biing-Jye Lee, Ming-Jiunn Jou