Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: An automatic power grid synthesis method and a computer readable recording medium for storing a program thereof for synthesizing power grid in a circuit area are provided. The circuit area has at least one power consuming module therein and at least one power pin disposed around the circuit area. The method includes the following steps. First, select at least one representative point in each power consuming module. The circuit area is divided into a plurality of regions according to the positions of the representative point(s) and the power pin. An overall power grid density of each region is calculated in accordance with the position of each power pin and the power consumption or current requirement at each representative point. Finally, the power grid synthesis is performed in each region according to the corresponding overall power grid density of the region.

Abstract: IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.

Abstract: A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.

Abstract: A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target cell is provided from the driving strength of a corresponding last level device. In this method, at least one candidate standard cell is searched in a standard cell library according to the last level device. Then, the driving strength of the target cell is interpolated between the driving strengths of the candidate standard cells to obtain the driving strength of the output pin of the target cell.

Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.

Abstract: A method for static power characterization of an analog integrated circuit includes detecting whether each of a plurality of input pins is electrically connected to a specific circuit; selecting a plurality of test benches of the static power characterization according to a number of the input pins electrically connected to the specific circuit; and processing the plurality of selected test benches of the static power characterization.

Abstract: An automatic power grid synthesis method and a computer readable recording medium for storing a program thereof for synthesizing power grid in a circuit area are provided. The circuit area has at least one power consuming module therein and at least one power pin disposed around the circuit area. The method includes the following steps. First, select at least one representative point in each power consuming module. The circuit area is divided into a plurality of regions according to the positions of the representative point(s) and the power pin. An overall power grid density of each region is calculated in accordance with the position of each power pin and the power consumption or current requirement at each representative point. Finally, the power grid synthesis is performed in each region according to the corresponding overall power grid density of the region.

Abstract: A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.

Abstract: A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target cell is provided from the driving strength of a corresponding last level device. In this method, at least one candidate standard cell is searched in a standard cell library according to the last level device. Then, the driving strength of the target cell is interpolated between the driving strengths of the candidate standard cells to obtain the driving strength of the output pin of the target cell.

Abstract: IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.

Abstract: A silicon chip capacitance measurement circuit including three pairs of completely matched MOS transistors divided into two symmetrical circuits. Capacitance of a capacitor within the silicon chip is measured using the difference in average charging current flowing from the measurement circuit via a left and a right capacitor. A power supply provides a constant voltage source to the measurement circuit. A current measuring device measures the current flowing from the power supply to the measurement circuit. A signal generator provides a group of three-phase non-overlapping signals to the measurement circuit. The capacitance measurement circuit is able to limit measurement error due to the return of different size negative currents leading to the transient switching of MOS transistors in the current measurement device so that accuracy of capacitance measurement improves.

Abstract: A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew.