Patents by Inventor Jyh-Ming Jong
Jyh-Ming Jong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7039323Abstract: An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.Type: GrantFiled: August 13, 2001Date of Patent: May 2, 2006Assignee: Sun Microsystems, Inc.Inventors: Jyh-Ming Jong, Drew G. Doblar, Daniel R. Cassiday
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Publication number: 20060009931Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.Type: ApplicationFiled: September 12, 2005Publication date: January 12, 2006Inventors: Brian Smith, Jue Wu, Jyh-Ming Jong, Wai Fong, Leo Yuan, Prabhansu Chakrabarti
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Patent number: 6944692Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.Type: GrantFiled: September 13, 2001Date of Patent: September 13, 2005Assignee: Sun Microsystems, Inc.Inventors: Brian L. Smith, Jue Wu, Jyh-Ming Jong, Wai Fong, Leo Yuan, Prabhansu Chakrabarti
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Patent number: 6937680Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.Type: GrantFiled: April 24, 2001Date of Patent: August 30, 2005Assignee: Sun Microsystems, Inc.Inventors: Wai Fong, Jyh-Ming Jong, Leo Yuan, Brian Smith, Prabhansu Chakrabarti
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Patent number: 6880118Abstract: A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.Type: GrantFiled: October 25, 2001Date of Patent: April 12, 2005Assignee: Sun Microsystems, Inc.Inventors: Cecilia T. Chen, Jyh-Ming Jong, Wai Fong, Leo Yuan, Brian L. Smith
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Patent number: 6853594Abstract: A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a divide-by-X-counter, where X is an integer greater than 1 and less than 129. The divide-by-X-counter has an input that is coupled to the output of the second comparator.Type: GrantFiled: July 22, 2003Date of Patent: February 8, 2005Assignee: Sun Microsystems, Inc.Inventors: Chung-Hsiao R. Wu, Jyh-Ming Jong
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Publication number: 20050018494Abstract: A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a divide-by-X-counter, where X is an integer greater than 1 and less than 129. The divide-by-X-counter has an input that is coupled to the output of the second comparator.Type: ApplicationFiled: July 22, 2003Publication date: January 27, 2005Inventors: Chung-Hsiao Wu, Jyh-Ming Jong
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Publication number: 20050018760Abstract: A device configured to recover and repeat source synchronous data. The device is configured to receive source synchronous data via a first interface and recover the received data utilizing a first clock signal which is generated to be approximately ninety degrees out of phase with the received clock signal. A second clock signal is generated to be in phase with the received source synchronous clock signal. The second clock signal is the utilized to select a newly generated clock signal and latched data for transmission in a source synchronous manner. The device is further configured to shift the phase of the generated first clock signal to be approximately ninety degrees out of phase with the received data signal.Type: ApplicationFiled: July 24, 2003Publication date: January 27, 2005Inventors: Brian Smith, Jyh-Ming Jong
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Patent number: 6737892Abstract: One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.Type: GrantFiled: December 18, 2000Date of Patent: May 18, 2004Assignee: Sun Microsystems, Inc.Inventors: Jyh-Ming Jong, Chung-Hsiao Wu, Prabhansu Chakrabarti, Leo Yuan
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Patent number: 6690191Abstract: A bi-directional output buffer includes active termination and separate driving and receiving impedances. The buffer has at least a driving mode and a receiving mode. In driving mode, the output impedance of the buffer is calibrated to a specified strength. In receiving mode, the buffer is calibrated to another specified impedance as an active termination. In addition, the buffer may be configured such that resistive components are shared in driving and receiving modes.Type: GrantFiled: December 21, 2001Date of Patent: February 10, 2004Assignee: Sun Microsystems, Inc.Inventors: Chung-Hsiao R. Wu, Jyh-Ming Jong
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Publication number: 20030189973Abstract: A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.Type: ApplicationFiled: April 5, 2002Publication date: October 9, 2003Inventors: Drew G. Doblar, Jyh-Ming Jong, Brian Smith, Jurgen Schulz
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Publication number: 20030117172Abstract: A bidirectional output buffer includes active termination and separate driving and receiving impedances. The buffer has at least a driving mode and a receiving mode. In driving mode, the output impedance of the buffer is calibrated to a specified strength. In receiving mode, the buffer is calibrated to another specified impedance as an active termination. In addition, the buffer may be configured such that resistive components are shared in driving and receiving modes.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventors: Chung-Hsiao R. Wu, Jyh-Ming Jong
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Publication number: 20030080769Abstract: A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.Type: ApplicationFiled: October 25, 2001Publication date: May 1, 2003Inventors: Cecilia T. Chen, Jyh-Ming Jong, Wai Fong, Leo Yuan, Brian L. Smith
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Apparatus for on-chip reference voltage generator for receivers in high speed single-ended data link
Patent number: 6542026Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.Type: GrantFiled: August 15, 2001Date of Patent: April 1, 2003Assignee: Sun Microsystems, Inc.Inventors: Chung-Hsiao R. Wu, Jyh-Ming Jong, Prabhansu Chakrabarti, Leo Yuan -
Publication number: 20030051086Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.Type: ApplicationFiled: September 13, 2001Publication date: March 13, 2003Inventors: Brian L. Smith, Jue Wu, Jyh-Ming Jong, Wai Fong, Leo Yuan, Prabhansu Chakrabarti
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APPARATUS FOR ON-CHIP REFERENCE VOLTAGE GENERATOR FOR RECEIVERS IN HIGH SPEED SINGLE-ENDED DATA LINK
Publication number: 20030034829Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.Type: ApplicationFiled: August 15, 2001Publication date: February 20, 2003Inventors: Chung-Hsiao R. Wu, Jyh-Ming Jong, Prabhansu Chakrabarti, Leo Yuan -
Publication number: 20030030878Abstract: An optical receiver for receiving a first input data signal and a second input data signal, the optical receiver comprising: a first photo-detector, the first photo-detector operable to receive the first input data signal and operable to output a first electrical signal; a second photo-detector, the second photo-detector operable to receive the second input data signal and operable to output a second electrical signal; a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive the first electrical signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; and a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first electrical signal and the second electrical signal.Type: ApplicationFiled: August 13, 2001Publication date: February 13, 2003Inventors: Jyh-Ming Jong, Drew G. Doblar, Daniel R. Cassiday
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Publication number: 20030030872Abstract: An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.Type: ApplicationFiled: August 13, 2001Publication date: February 13, 2003Inventors: Jyh-Ming Jong, Drew G. Doblar, Daniel R. Cassiday
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Patent number: 6518792Abstract: A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized.Type: GrantFiled: June 11, 2001Date of Patent: February 11, 2003Assignee: Sun Microsystems, Inc.Inventors: Jyh-Ming Jong, Prabhansu Chakrabarti, Leo Yuan
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Patent number: 6512704Abstract: A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a flip-flop. The flip-flop has a preset input that is coupled to the output of the second comparator. The flip-flop has a clock input that is coupled to the output of the delay element.Type: GrantFiled: September 14, 2001Date of Patent: January 28, 2003Assignee: Sun Microsystems, Inc.Inventors: Chung-Hsiao R. Wu, Jyh-Ming Jong, Lee A. Warner, Jurgen M. Schulz