Abstract: The present invention provides a solar cell including: at least one rear electrode, at least one solar main body layer, and at least one upper electrode. The at least one solar main body layer surrounds the at least one rear electrode. The at least one upper electrode surrounds the at least one solar main body layer. Furthermore, the present invention provides a method for manufacturing the solar cell. The method includes the following steps: forming at least one rear electrode base (substrate); forming at least one solar main body layer surrounding the at least one rear electrode base (substrate); and forming at least one upper electrode surrounding the at least one solar main body layer.

Abstract: The semiconductor device with a ?-shaped semiconductor conductive layer manufactured by the manufacturing method thereof utilizes two pathways of the ?-shaped semiconductor conductive layer connected to the silicon layer of a silicon-on-insulator (SOI) substrate for heat dissipation, so as to reduce the self-heating effects (SHEs). Furthermore, the semiconductor device of the invention utilizes the self-aligned technique to form a self-aligned structure with a gate unit and the silicon layer, so that the process is simple, the production cost is reduced, the compacted ability and the yield are improved, the off current and short-channel effects (SCEs) are still similar to a conventional UTSOI MOSFET, and the stability and the reliability are therefore superior.

Abstract: The present invention relates to a trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell and a method for making the same. A source and a drain are utilized to each connect to one of two semiconductor conductive units on an external side of a main body having a plurality of semiconductor conductive units, and the semiconductor conductive units are utilized to accumulate electric charges generated from the drain so as to decrease a threshold voltage. In addition, the DRAM cell only uses one field effect transistor (FET) device (1T), has characteristics of the conventional 1T-DRAM, and has higher integration density. Moreover, the process of the invention is simple, so the production cost can be reduced.

Abstract: The semiconductor device with a ?-shaped semiconductor conductive layer manufactured by the manufacturing method thereof utilizes two pathways of the ?-shaped semiconductor conductive layer connected to the silicon layer of a silicon-on-insulator (SOI) substrate for heat dissipation, so as to reduce the self-heating effects (SHEs). Furthermore, the semiconductor device of the invention utilizes the self-aligned technique to form a self-aligned structure with a gate unit and the silicon layer, so that the process is simple, the production cost is reduced, the compacted ability and the yield are improved, the off current and short-channel effects (SCEs) are still similar to a conventional UTSOI MOSFET, and the stability and the reliability are therefore superior.

Abstract: The present invention relates to a trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell and a method for making the same. A source and a drain are utilized to each connect to one of two semiconductor conductive units on an external side of a main body having a plurality of semiconductor conductive units, and the semiconductor conductive units are utilized to accumulate electric charges generated from the drain so as to decrease a threshold voltage. In addition, the DRAM cell only uses one field effect transistor (FET) device (1T), has characteristics of the conventional 1T-DRAM, and has higher integration density. Moreover, the process of the invention is simple, so the production cost can be reduced.